US5579256A
Expired / Lapsed
US
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Semiconductor memory device and defect remedying method thereof
Assignee: Hitachi Solutions Technology Ltd
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Filing: 1995-05-31
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Granted: 1996-11-26
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Expires: 2015-05-31
Abstract
Abstract Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.
Inventors
- 👤 Kazuhiko Kajigaya
- 👤 Kazuyuki Miyazawa
- 👤 Manabu Tsunozaki
- 👤 Kazuyoshi Oshima
- 👤 Takashi Yamazaki
- 👤 Yuji Sakai
- 👤 Jiro Sawada
- 👤 Yasunori Yamaguchi
- 👤 Tetsurou Matsumoto
- 👤 Shinji Udo
- 👤 Hiroshi Yoshioka
- 👤 Hirokazu Saito
- 👤 Mitsuhiro Takano
- 👤 Makoto Morino
- 👤 Sinichi Miyatake
- 👤 Eiji Miyamoto
- 👤 Yasuhiro Kasama
- 👤 Akira Endo
- 👤 Ryoichi Hori
- 👤 Jun Etoh
- 👤 Masashi Horiguchi
- 👤 Shinichi Ikenaga
- 👤 Atsushi Kumata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 01:01
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/02; G11C5/025; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; H; H10; H10W; H10W72/00; H10W72/90; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/551; H10W72/552; H10W72/5522; H10W72/59; H10W72/851; H10W72/853; H10W72/865; H10W72/931; H10W72/932; H10W72/934; H10W72/951; H10W72/952; H10W74/00; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756; Y; Y10; Y10S; Y10S257/00; Y10S257/908
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
231 words
A semiconductor memory device formed in a quadrilateral region on a semiconductor substrate, said quadrilateral region comprising: a first region extending in a direction of a first center line which intersects a middle point of a short side of said quadrilateral region; a second region extending in a direction of a second center line which intersects a middle point of a long side of said quadrilateral region; and a third region, a fourth region, a fifth region and a sixth region which are four divided regions divided by said first region and said second region from said quadrilateral region, said device comprising: a first memory array, a second memory array, a third memory array and a fourth memory array each of which is formed in a corresponding one of said third region, said fourth region, said fifth region and said sixth region and each of which comprises a plurality of memory cells and a plurality of sense amplifiers; a peripheral circuit formed in at least one of said first region and said second region, said peripheral circuit operating in connection with operations of said first memory array, said second memory array, said third memory array and said fourth memory array; and a plurality of bonding pads formed extending in a direction of said first center line in said first region, said plurality of bonding pads being arranged in a zigzag formation.
Claim 2
Dependent Claim
231 words
A semiconductor memory device formed in a quadrilateral region on a semiconductor substrate, said quadrilateral region comprising: a first region extending in a direction of a first center line which intersects a middle point of a short side of said quadrilateral region; a second region extending in a direction of a second center line which intersects a middle point of a long side of said quadrilateral region; and a third region, a fourth region, a fifth region and a sixth region which are four divided regions divided by said first region and said second region from said quadrilateral region, said device comprising: a first memory array, a second memory array, a third memory array and a fourth memory array each of which is formed in a corresponding one of said third region, said fourth region, said fifth region and said sixth region and each of which comprises a plurality of memory cells and a plurality of sense amplifiers; a peripheral circuit formed in at least one of said first region and said second region, said peripheral circuit operating in connection with operations of said first memory array, said second memory array, said third memory array and said fourth memory array; and a plurality of bonding pads formed extending in a direction of said first center line in said first region, said plurality of bonding pads being arranged in a zigzag formation.
Claim 3
Dependent Claim
48 words
A semiconductor memory device according to claim 1, wherein said plurality of bonding pads are coupled to at least a corresponding one of a plurality of leads, and wherein said semiconductor substrate and one part of each of said plurality of leads are encapsulated in a molding material.
Claim 4
Dependent Claim
73 words
A semiconductor memory device according to claim 2, wherein said plurality of bonding pads comprises a plurality of first bonding pads and a plurality of second bonding pads, said plurality of first bonding pads being formed in a line, said plurality of second bonding pads being formed in a line, and said plurality of first bonding pads and said plurality of second bonding pads being formed on different imaginary lines from each other.
Claim 5
Dependent Claim
132 words
A semiconductor memory device according to claim 1, wherein each of said first memory array, said second memory array, said third memory array and said fourth memory array comprises a plurality of memory mats, each of said plurality of memory mats comprising: a plurality of word lines extending in a first direction; a plurality of data lines extending in a second direction which is perpendicular to said first direction; and a first decoder selecting at least one of said plurality of word lines, wherein each of said plurality of memory cells comprised in said first memory array, said second memory array, said third memory array and said fourth memory array is coupled to a corresponding one of said plurality of word lines and a corresponding one of said plurality of data lines.
Claim 6
Dependent Claim
45 words
A semiconductor memory device according to claim 3, wherein said plurality of leads comprise a first lead receiving a first voltage from an outside of said device, and wherein at least two of said plurality of first bonding pads are coupled to said first lead.
Claim 7
Dependent Claim
53 words
A semiconductor memory device according to claim 5, wherein said plurality of leads comprise a second lead receiving a second voltage from an outside of said device, said second voltage differing from said first voltage, and wherein at least two of said plurality of second bonding pads are coupled to said second lead.
References Cited (Backward Citations)
US4951112A
Cited
US5287000A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-26 | 2000-05-27 | 2000-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-26 | 2004-05-27 | 2004-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-26 | 2008-05-27 | 2008-11-26 | $7700.00 | Window Closed / Lapsed |