US6160744A
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Semiconductor memory device and defect remedying method thereof
Assignee: Hitachi Ltd
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Filing: 1999-07-27
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Granted: 2000-12-12
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Expires: 2019-07-27
Abstract
Abstract Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.
Inventors
- 👤 Kazuhiko Kajigaya
- 👤 Kazuyuki Miyazawa
- 👤 Manabu Tsunozaki
- 👤 Kazuyoshi Oshima
- 👤 Takashi Yamazaki
- 👤 Yuji Sakai
- 👤 Jiro Sawada
- 👤 Yasunori Yamaguchi
- 👤 Tetsurou Matsumoto
- 👤 Shinji Udo
- 👤 Hiroshi Yoshioka
- 👤 Hirokazu Saito
- 👤 Mitsuhiro Takano
- 👤 Makoto Morino
- 👤 Sinichi Miyatake
- 👤 Eiji Miyamoto
- 👤 Yasuhiro Kasama
- 👤 Akira Endo
- 👤 Ryoichi Hori
- 👤 Jun Etoh
- 👤 Masashi Horiguchi
- 👤 Shinichi Ikenaga
- 👤 Atsushi Kumata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 13:59
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/02; G11C5/025; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C5/06; G11C5/063; H; H10; H10W; H10W72/00; H10W72/90; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/551; H10W72/552; H10W72/5522; H10W72/59; H10W72/851; H10W72/853; H10W72/865; H10W72/931; H10W72/932; H10W72/934; H10W74/00; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 63
Claim 1
Independent Claim
108 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; and dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; wherein each of said dynamic memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor of each of said dynamic memory cells; wherein a number of refresh cycles for refreshing said dynamic memory cells of n bits is √n or more in at least one operation mode of the semiconductor memory; and wherein said n bits are 16 megabits or more.
Claim 2
Dependent Claim
108 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; and dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; wherein each of said dynamic memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor of each of said dynamic memory cells; wherein a number of refresh cycles for refreshing said dynamic memory cells of n bits is √n or more in at least one operation mode of the semiconductor memory; and wherein said n bits are 16 megabits or more.
Claim 3
Dependent Claim
39 words
A semiconductor memory according to claim 1, wherein said semiconductor memory has a first operation mode in which the number of refresh cycles is √n and a second operation mode in which the number of refresh cycles is √n/2.
Claim 4
Dependent Claim
17 words
A semiconductor memory according to claim 2, wherein said second operation mode is a CBR refresh mode.
Claim 5
Dependent Claim
28 words
A semiconductor memory according to claim 1, wherein said number of refresh cycles is a number in a progression expressed as √n, 2n, 4√n, - - - .
Claim 6
Dependent Claim
113 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; and dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; wherein each of said dynamic memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor of each of said memory cells; wherein a number of refresh cycles for refreshing said dynamic memory cells of n bits is a number in a progression expressed as √n, 2√n, 4n, - - - in at least on operation mode; and wherein said n bits are 16 megabits or more.
Claim 7
Dependent Claim
113 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; and dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; wherein each of said dynamic memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor of each of said memory cells; wherein a number of refresh cycles for refreshing said dynamic memory cells of n bits is a number in a progression expressed as √n, 2√n, 4n, - - - in at least on operation mode; and wherein said n bits are 16 megabits or more.
Claim 8
Dependent Claim
86 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; and dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; wherein each of said dynamic memory cells uses a stacked capacitor; wherein a number of refresh cycles for refreshing said dynamic memory cells of n bits is √n or more in at least one operation mode of the semiconductor memory; and wherein said n bits are 16 megabits or more.
Claim 9
Dependent Claim
86 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; and dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; wherein each of said dynamic memory cells uses a stacked capacitor; wherein a number of refresh cycles for refreshing said dynamic memory cells of n bits is √n or more in at least one operation mode of the semiconductor memory; and wherein said n bits are 16 megabits or more.
Claim 10
Dependent Claim
39 words
A semiconductor memory according to claim 6, wherein said semiconductor memory has a first operation mode in which a number of refresh cycles is √n and a second operation mode in which a number of refresh cycles is √n/2.
Claim 11
Dependent Claim
16 words
A semiconductor memory according to claim 7, wherein said second operation mode is a CBR refresh.
Claim 12
Dependent Claim
29 words
A semiconductor memory according to claim 6, wherein said number of refresh cycles is one of numbers in a progression expressed as √n, 2√n, 4√n, - - - .
Claim 13
Dependent Claim
96 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; and dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; wherein each of said dynamic memory cells uses a stacked capacitor; wherein a number of refresh cycles for refreshing said dynamic memory cells of n bits is a number in a progression expressed as √n, 2√n, 4√n, - - - in at least one operation mode of the semiconductor memory; and wherein said n bits are 16 megabits or more.
Claim 14
Dependent Claim
96 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; and dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; wherein each of said dynamic memory cells uses a stacked capacitor; wherein a number of refresh cycles for refreshing said dynamic memory cells of n bits is a number in a progression expressed as √n, 2√n, 4√n, - - - in at least one operation mode of the semiconductor memory; and wherein said n bits are 16 megabits or more.
Claim 15
Dependent Claim
85 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; and dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; wherein a number of refresh cycles for refreshing said dynamic memory cells of n bits is a number in a progression expressed as 2√n, 4√n, 8√n, - - - in at least one operation mode of the semiconductor memory; and wherein said n bits are 16 megabits or more.
Claim 16
Dependent Claim
85 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; and dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; wherein a number of refresh cycles for refreshing said dynamic memory cells of n bits is a number in a progression expressed as 2√n, 4√n, 8√n, - - - in at least one operation mode of the semiconductor memory; and wherein said n bits are 16 megabits or more.
Claim 17
Dependent Claim
72 words
A semiconductor memory according to claim 11, wherein each of said dynamic memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor of each of said memory cells; and wherein said semiconductor memory has a first operation mode in which a number of refresh cycles is 2√n and a second operation mode in which a number of refresh cycles is √n/2.
Claim 18
Dependent Claim
88 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein said n bits are 16 megabits or more; wherein the number of activated sense amplifiers per one memory access is √n or lower; and a plurality of bits obtained through said activated sense amplifiers are output as a data.
Claim 19
Dependent Claim
88 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein said n bits are 16 megabits or more; wherein the number of activated sense amplifiers per one memory access is √n or lower; and a plurality of bits obtained through said activated sense amplifiers are output as a data.
Claim 20
Dependent Claim
34 words
A semiconductor memory according to claim 13, wherein said data is m bits data, wherein m is a number in a progression expressed as 2 k , k=1, 2, 3, - - - .
Claim 21
Dependent Claim
19 words
A semiconductor memory according to claim 14, further comprising: m output pins for outputting said m bits in parallel.
Claim 22
Dependent Claim
18 words
A semiconductor memory according to claim 14, further comprising: an output pin for outputting said m bits serially.
Claim 23
Dependent Claim
22 words
A semiconductor memory according to claim 16, wherein said m bits are selected sequentially on the basis of an internal column address.
Claim 24
Dependent Claim
39 words
A semiconductor memory according to claim 14, wherein each of said dynamic memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor of each of said memory cells.
Claim 25
Dependent Claim
81 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; and dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; wherein said n bits are 16 megabits or more; wherein the number of dynamic memory cells connected to a selected word line per one memory access is √n or lower; and a plurality of bits obtained through said activated sense amplifiers are output as data.
Claim 26
Dependent Claim
81 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; and dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; wherein said n bits are 16 megabits or more; wherein the number of dynamic memory cells connected to a selected word line per one memory access is √n or lower; and a plurality of bits obtained through said activated sense amplifiers are output as data.
Claim 27
Dependent Claim
32 words
A semiconductor memory according to claim 19, wherein said data is m bits data, wherein m is a number in a progression expressed as 2k, k=1, 2, 3, - - - .
Claim 28
Dependent Claim
18 words
A semiconductor memory according to claim 20, further comprising: an output pin for outputting said m bits serially.
Claim 29
Dependent Claim
39 words
A semiconductor memory according to claim 20, wherein each of said dynamic memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor of each of said memory cells.
Claim 30
Dependent Claim
103 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activated sense amplifiers per cycle in a second operation mode; and wherein a first cycle time in said first operation mode is longer than a second cycle time in said second operation mode.
Claim 31
Dependent Claim
103 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activated sense amplifiers per cycle in a second operation mode; and wherein a first cycle time in said first operation mode is longer than a second cycle time in said second operation mode.
Claim 32
Dependent Claim
29 words
A semiconductor memory according to claim 23, wherein said n bits are 16 megabits or more; and wherein said first number is √n and said second number is 2√n.
Claim 33
Dependent Claim
17 words
A semiconductor memory according to claim 23, wherein a refresh is performed in said second operation mode.
Claim 34
Dependent Claim
18 words
A semiconductor memory according to claim 25, wherein a memory access is performed in said first operation mode.
Claim 35
Dependent Claim
16 words
A semiconductor memory according to claim 26, wherein said second operation mode is a CBR refresh.
Claim 36
Dependent Claim
151 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; a plurality of sense amplifiers connected to said plurality of bit lines; a first circuit which activates one or more of said plurality of sense amplifiers; and a second circuit which forms a first timing signal and a second timing signal following said first timing signal; wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activated sense amplifiers per cycle in a second operation mode; wherein said first circuit includes a power switch which is controlled by said first timing signal in said first operation mode; and wherein said power switch is controlled by said second timing signal in said second operation mode.
Claim 37
Dependent Claim
151 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; a plurality of sense amplifiers connected to said plurality of bit lines; a first circuit which activates one or more of said plurality of sense amplifiers; and a second circuit which forms a first timing signal and a second timing signal following said first timing signal; wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activated sense amplifiers per cycle in a second operation mode; wherein said first circuit includes a power switch which is controlled by said first timing signal in said first operation mode; and wherein said power switch is controlled by said second timing signal in said second operation mode.
Claim 38
Dependent Claim
29 words
A semiconductor memory according to claim 28, wherein said n bits are 16 megabits or more; and wherein said first number is √n and said second number is 2√n.
Claim 39
Dependent Claim
16 words
A semiconductor memory according to claim 29, wherein said second operation mode is a CBR refresh.
Claim 40
Dependent Claim
138 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activates sense amplifiers per cycle in a second operation mode; wherein said activated sense amplifiers take a first charging time to set corresponding bit lines to a predetermined voltage level in said first operation mode and a second charging time to set corresponding bit lines to said predetermined voltage level in said second operation mode, and wherein said first charging time is longer than said second charging time.
Claim 41
Dependent Claim
138 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activates sense amplifiers per cycle in a second operation mode; wherein said activated sense amplifiers take a first charging time to set corresponding bit lines to a predetermined voltage level in said first operation mode and a second charging time to set corresponding bit lines to said predetermined voltage level in said second operation mode, and wherein said first charging time is longer than said second charging time.
Claim 42
Dependent Claim
28 words
A semiconductor memory according to claim 31, wherein said n bits are 16 megabits or more, and wherein said first is √n and said second number is 2√n.
Claim 43
Dependent Claim
16 words
A semiconductor memory according to claim 32, wherein said second operation mode is a CBR refresh.
Claim 44
Dependent Claim
172 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; a plurality of sense amplifiers connected to said plurality of bit lines; a first circuit which activates one or more of said plurality of sense amplifiers; and a second circuit which forms a first timing signal and a second timing signal following said first timing signal; wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activated sense amplifiers per cycle in a second operation mode; wherein a first cycle time in said first operation mode is longer than a second cycle time in said second operation; wherein said first circuit includes a power switch which is controlled by said first timing signal in said first operation mode; and wherein said power switch is controlled by said second timing signal in said second operation mode.
Claim 45
Dependent Claim
172 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; a plurality of sense amplifiers connected to said plurality of bit lines; a first circuit which activates one or more of said plurality of sense amplifiers; and a second circuit which forms a first timing signal and a second timing signal following said first timing signal; wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activated sense amplifiers per cycle in a second operation mode; wherein a first cycle time in said first operation mode is longer than a second cycle time in said second operation; wherein said first circuit includes a power switch which is controlled by said first timing signal in said first operation mode; and wherein said power switch is controlled by said second timing signal in said second operation mode.
Claim 46
Dependent Claim
29 words
A semiconductor memory according to claim 34, wherein said n bits are 16 megabits or more, and wherein said first number is √n and said second number is 2√n.
Claim 47
Dependent Claim
159 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activated sense amplifiers per cycle in a second operation mode; wherein a first cycle time in said first operation mode is longer than a second cycle time in said second operation; wherein said activated sense amplifiers take a first charging time to set corresponding bit lines to a predetermined voltage level in said first operation mode and a second charging time to set corresponding bit lines to said predetermined voltage level in said second operation mode; and wherein said first charging time is longer than said second charging time.
Claim 48
Dependent Claim
159 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activated sense amplifiers per cycle in a second operation mode; wherein a first cycle time in said first operation mode is longer than a second cycle time in said second operation; wherein said activated sense amplifiers take a first charging time to set corresponding bit lines to a predetermined voltage level in said first operation mode and a second charging time to set corresponding bit lines to said predetermined voltage level in said second operation mode; and wherein said first charging time is longer than said second charging time.
Claim 49
Dependent Claim
29 words
A semiconductor memory according to claim 36, wherein said n bits are 16 megabits or more, and wherein said first number is √n and said second number is 2√n.
Claim 50
Dependent Claim
229 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; a plurality of sense amplifiers connected to said plurality of bit lines; a first circuit which activates one or more of said plurality of sense amplifiers; and a second circuit which forms a first timing signal and a second timing signal following said first timing signal; wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activated sense amplifiers per cycle in a second operation mode; wherein a first cycle time in said first operation mode is longer than a second cycle time in said second operation; wherein said first circuit includes a power switch which is controlled by said first timing signal in said first operation mode; wherein said power switch is controlled by said second timing signal in said second operation mode; wherein said activated sense amplifiers take a first charging time to set corresponding bit lines to a predetermined voltage level in said first operation mode and a second charging time to set corresponding bit lines to said predetermined voltage level in said second operation mode; and wherein said first charging time is longer than said second charging time.
Claim 51
Dependent Claim
229 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits arranged at crossings of said plurality of word lines and said plurality of bit lines; a plurality of sense amplifiers connected to said plurality of bit lines; a first circuit which activates one or more of said plurality of sense amplifiers; and a second circuit which forms a first timing signal and a second timing signal following said first timing signal; wherein a first number of activated sense amplifiers per cycle in a first operation mode is larger than a second number of activated sense amplifiers per cycle in a second operation mode; wherein a first cycle time in said first operation mode is longer than a second cycle time in said second operation; wherein said first circuit includes a power switch which is controlled by said first timing signal in said first operation mode; wherein said power switch is controlled by said second timing signal in said second operation mode; wherein said activated sense amplifiers take a first charging time to set corresponding bit lines to a predetermined voltage level in said first operation mode and a second charging time to set corresponding bit lines to said predetermined voltage level in said second operation mode; and wherein said first charging time is longer than said second charging time.
Claim 52
Dependent Claim
29 words
A semiconductor memory according to claim 38, wherein said n bits are 16 megabits or more, and wherein said first number is √n and said second number is 2√n.
Claim 53
Dependent Claim
90 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein each of said dynamic memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor of each of said memory cells; wherein the number of activated sense amplifiers per one memory access is √n or lower; and wherein said n bits are 16 megabits or more.
Claim 54
Dependent Claim
90 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein each of said dynamic memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor of each of said memory cells; wherein the number of activated sense amplifiers per one memory access is √n or lower; and wherein said n bits are 16 megabits or more.
Claim 55
Dependent Claim
101 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein each of said dynamic memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor of each of said memory cells; wherein the number of activated sense amplifiers per one memory access is a number in a progression expressed as √n, √n/2, √n/4, - - - ; and wherein said n bits are 16 megabits or more.
Claim 56
Dependent Claim
101 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein each of said dynamic memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor of each of said memory cells; wherein the number of activated sense amplifiers per one memory access is a number in a progression expressed as √n, √n/2, √n/4, - - - ; and wherein said n bits are 16 megabits or more.
Claim 57
Dependent Claim
69 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein each of said dynamic memory cells uses a stacked capacitor; wherein the number of activated sense amplifiers per one memory access is √n or lower; and wherein said n bits are 16 megabits or more.
Claim 58
Dependent Claim
69 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein each of said dynamic memory cells uses a stacked capacitor; wherein the number of activated sense amplifiers per one memory access is √n or lower; and wherein said n bits are 16 megabits or more.
Claim 59
Dependent Claim
80 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein each of said dynamic memory cells uses a stacked capacitor; wherein the number of activated sense amplifiers per one memory access is a number in a progression expressed as √n, √n/2, √n/4, - - - ; and wherein said n bits are 16 megabits or more.
Claim 60
Dependent Claim
80 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein each of said dynamic memory cells uses a stacked capacitor; wherein the number of activated sense amplifiers per one memory access is a number in a progression expressed as √n, √n/2, √n/4, - - - ; and wherein said n bits are 16 megabits or more.
Claim 61
Dependent Claim
69 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein the number of activated sense amplifiers per one memory access is a number in a progression expressed as √n/2, √n/4, √n/8, - - - ; and wherein said n bits are 16 megabits or more.
Claim 62
Dependent Claim
69 words
A semiconductor memory comprising: a plurality of word lines; a plurality of bit lines; dynamic memory cells of n bits; and a plurality of sense amplifiers connected to said plurality of bit lines; wherein the number of activated sense amplifiers per one memory access is a number in a progression expressed as √n/2, √n/4, √n/8, - - - ; and wherein said n bits are 16 megabits or more.
Claim 63
Dependent Claim
39 words
A semiconductor memory according to claim 44, wherein each of said dynamic memory cells has a stereoscopic structure which does not use a substrate as an electrode of an information charge storage capacitor of each of said memory cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-12 | 2004-06-12 | 2004-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-12 | 2008-06-12 | 2008-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-12 | 2012-06-12 | 2012-12-12 | $7700.00 | Window Closed / Lapsed |