Patent US6515546B2 successfully refreshed from Google Patents.
US6515546B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bias circuit for use with low-voltage power supply
Assignee: Skyworks Solutions Inc
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Filing: 2001-06-06
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Granted: 2003-02-04
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Expires: 2021-06-06
Abstract
Abstract A transistor bias circuit is provided that is capable of operating from a power supply voltage that is slightly higher than twice the base-emitter voltage of the transistor to be biased. The bias circuit includes a transistor connected in a current-mirror configuration with the transistor to be biased. A feedback circuit maintains die mirrored current at a constant level. The gain of the feedback circuit is improved by the addition of a non-inverting amplifier within the feedback circuit.
Inventors
- 👤 Henry Z. Liwinski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:03
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/265; H; H03; H03F; H03F1/00; H03F1/30; H03F1/302; H03F3/00; H03F3/34; H03F3/343; H03F2200/00; H03F2200/513
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
255 words
A circuit for biasing a first transistor having a control terminal, current-sink terminal, and current-source terminal and capable of operating from a power supply having positive and ground terminals, the circuit comprising: a. a second transistor having a control terminal, current-sink terminal and current-source terminal, i. wherein the control terminal of said second transistor is connected to the control terminal of such first transistor in a current-mirror configuration, and ii. wherein the current-sink terminal of said second transistor is connected to the ground terminal of such power supply; b. a first resistor connected between the current-source terminal of said second transistor and the positive terminal of such power supply; c. a feedback circuit, including i. a non-inverting amplifier having input and output ports, (1) wherein the input port of said non-inverting amplifier is connected to the node formed by said first resistor and the current-source terminal of said second transistor; and ii. a feedback transistor having a control terminal, current-sink terminal, and current-source terminal, (1) wherein the control terminal of said feedback transistor is connected to the output port of said non-inverting amplifier, (2) wherein the current-sink terminal of said feedback transistor is connected to the node formed by the connection of said second transistor to such first transistor, and (3) wherein the current-source terminal of said feedback transistor is connected to the positive terminal of such power supply, whereby said non-inverting amplifier increases the gain of the feedback circuit so that the bias circuit is relatively insensitive to fluctuations in supply voltage or temperature.
Claim 2
Dependent Claim
255 words
A circuit for biasing a first transistor having a control terminal, current-sink terminal, and current-source terminal and capable of operating from a power supply having positive and ground terminals, the circuit comprising: a. a second transistor having a control terminal, current-sink terminal and current-source terminal, i. wherein the control terminal of said second transistor is connected to the control terminal of such first transistor in a current-mirror configuration, and ii. wherein the current-sink terminal of said second transistor is connected to the ground terminal of such power supply; b. a first resistor connected between the current-source terminal of said second transistor and the positive terminal of such power supply; c. a feedback circuit, including i. a non-inverting amplifier having input and output ports, (1) wherein the input port of said non-inverting amplifier is connected to the node formed by said first resistor and the current-source terminal of said second transistor; and ii. a feedback transistor having a control terminal, current-sink terminal, and current-source terminal, (1) wherein the control terminal of said feedback transistor is connected to the output port of said non-inverting amplifier, (2) wherein the current-sink terminal of said feedback transistor is connected to the node formed by the connection of said second transistor to such first transistor, and (3) wherein the current-source terminal of said feedback transistor is connected to the positive terminal of such power supply, whereby said non-inverting amplifier increases the gain of the feedback circuit so that the bias circuit is relatively insensitive to fluctuations in supply voltage or temperature.
Claim 3
Dependent Claim
21 words
The circuit according to claim 1 , wherein said second transistor is one of a BJT, an HBT, and a FET.
Claim 4
Dependent Claim
21 words
The circuit according to claim 1 , wherein said feedback transistor is one of a BJT, an HBT, and a FET.
Claim 5
Dependent Claim
29 words
The circuit according to claim 1 , further comprising a second resistor coupled between the current-sink terminal of said feedback transistor and the ground terminal of such power supply.
Claim 6
Dependent Claim
52 words
The circuit according to claim 1 , further comprising: a. a third resistor coupled between the control terminal of such first transistor and the current-sink terminal of said feedback transistor; and b. a fourth resistor coupled between the control terminal of said second transistor and the current-sink terminal of said feedback transistor.
Claim 7
Dependent Claim
24 words
The circuit according to claim 1 wherein said non-inverting amplifier comprises two cascaded transistors, each having a control terminal, current-sink terminal, and current-source terminal.
Claim 8
Dependent Claim
37 words
The circuit according to claim 6 , wherein said non-inverting amplifier further comprises: a. two resistors, each coupled between the current-source terminal of one of said cascaded transistors, respectively, and the positive terminal of such power supply.
Claim 9
Dependent Claim
37 words
The circuit according to claim 7 , wherein said non-inverting amplifier further comprises: a. two resistors, each coupled between the current-sink terminal of one of said cascaded transistors, respectively, and the ground terminal of such power supply.
Claim 10
Independent Claim
84 words
A method of biasing a first transistor having a control terminal, a current-sink terminal, and a current-source terminal and capable of operating from a power supply having positive and ground terminals via a bias circuit including a second transistor connected in a current-mirror configuration with the first transistor, the method comprising the steps of: a. monitoring an electrical characteristic at the current-source terminal of the second transistor; b. amplifying the monitored characteristic; and c. feeding back the amplified characteristic to control the second transistor.
Claim 11
Independent Claim
84 words
A method of biasing a first transistor having a control terminal, a current-sink terminal, and a current-source terminal and capable of operating from a power supply having positive and ground terminals via a bias circuit including a second transistor connected in a current-mirror configuration with the first transistor, the method comprising the steps of: a. monitoring an electrical characteristic at the current-source terminal of the second transistor; b. amplifying the monitored characteristic; and c. feeding back the amplified characteristic to control the second transistor.
Claim 12
Dependent Claim
16 words
The method of claim 9 , wherein the electrical characteristic is one of current and voltage.
Claim 13
Dependent Claim
31 words
The method of claim 9 , wherein the step of amplifying comprises the steps of inverting the characteristic and then re-inverting the characteristic, such that a non-inverted amplified characteristic is produced.
Claim 14
Dependent Claim
15 words
The method of claim 9 , further comprising the step of level-shifting the monitored characteristic.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-02-03 | 2006-08-05 | 2007-02-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-02-03 | 2010-08-05 | 2011-02-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-02-03 | 2014-08-05 | 2015-02-04 | $7700.00 | Window Closed / Lapsed |