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US4462005A Expired / Lapsed US ⏱️ 0.0 years remaining

Current mirror circuit

Assignee: Toshiba Corp
•
Filing: 1982-06-11
•
Granted: 1984-07-24
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Expires: 2002-06-11
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Abstract

Abstract A current mirror circuit in which error between input current and output current is small and which can operate with low voltage. First and second current mirror transistors of a first conductivity type have their emitters each connected to a power supply, their bases connected together and their collectors connected to an input terminal and an output terminal respectively. A current amplification factor compensating third transistor of the first conductivity type is provided which has its emitter connected to the bases of the first and second transistors and its collector connected to a reference potential point. A fourth transistor of a second conductivity type is provided for level shifting. This transistor has its collector connected to the emitters of the first and second transistors, its emitter connected to the base of the third transistor and its base connected to the collector of the first transistor. A current source is connected between the third transistor and the reference potential point.

Inventors

  • 👤 Hiromi Kusakabe
  • 👤 Yoshihiro Yoshida

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 21:25
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/265

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 205 words
A current mirror circuit comprising: a first transistor of a first conductivity type having a first emitter, a first base and a first collector, the first emitter and first collector being connected to a power supply and a current input terminal, respectively; a second transistor of the first conductivity type having a second emitter, a second base and a second collector, the second emitter, second collector and second base being connected to the power supply, a current output terminal and the first base, respectively; voltage level shift means including a third transistor of the first conductivity type having a third emitter, a third base and a third collector, the third emitter being connected to the bases of said first and second transistors and the third collector being connected to a reference potential; a fourth transistor of a second conductivity type having a fourth emitter, a fourth base and a fourth collector, the fourth collector, the fourth emitter and the fourth base being connected to the power supply, the third base and the first collector, respectively; a current source connected between the reference potential and the third base; and a resistor connected between the emitter of said fourth transistor and the base of said third transistor.
Claim 2
Dependent Claim 205 words
A current mirror circuit comprising: a first transistor of a first conductivity type having a first emitter, a first base and a first collector, the first emitter and first collector being connected to a power supply and a current input terminal, respectively; a second transistor of the first conductivity type having a second emitter, a second base and a second collector, the second emitter, second collector and second base being connected to the power supply, a current output terminal and the first base, respectively; voltage level shift means including a third transistor of the first conductivity type having a third emitter, a third base and a third collector, the third emitter being connected to the bases of said first and second transistors and the third collector being connected to a reference potential; a fourth transistor of a second conductivity type having a fourth emitter, a fourth base and a fourth collector, the fourth collector, the fourth emitter and the fourth base being connected to the power supply, the third base and the first collector, respectively; a current source connected between the reference potential and the third base; and a resistor connected between the emitter of said fourth transistor and the base of said third transistor.
Claim 3
Dependent Claim 49 words
The current mirror circuit according to claim 1 wherein a fifth transistor of the first conductivity type is provided which has its emitter connected to the collector of said second transistor, its collector connected to said output terminal and its base connected to the emitter of said fourth transistor.
Claim 4
Dependent Claim 26 words
The current mirror circuit according to claim 1 or 2 wherein the first conductivity type is PNP type and the second conductivity type is NPN type.

References Cited (Backward Citations)

US3813607A Cited
DE3114877A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-07-24 1988-01-23 1988-07-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-07-24 1992-01-23 1992-07-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-07-24 1996-01-23 1996-07-24 $7700.00 Window Closed / Lapsed

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