RF amplifier circuit

Claim 2

An amplifier circuit having an input terminal, an output terminal, a power supply terminal, and a control node, the amplifier circuit comprising: means in the form of first, second, and third transistors interconnected in a modified current source configuration with first, second, and third resistors and a matching circuit for producing a desired bias current according to the magnitude of a control voltage coupled to the control node while producing an amplified output radio frequency signal at the output terminal from an input radio frequency signal coupled to the input terminal, each of the first, second, and third transistors having a base, an emitter, and a collector; the first transistor having its collector connected to a first common node, its base connected to a second common node, and its emitter connected to a common ground; the second transistor having its base connected to the first common node and its collector connected to the power supply terminal; the third transistor having its base connected to the second common node and its emitter connected to the common ground; the first resistor being connected between the first common node and the control node; the second resistor being connected between the emitter of the second transistor and the second common node; the third resistor being connected between the second common node and the common ground; and the matching circuit including means connected to the collector of the third transistor, the power supply terminal, and the output terminal for presenting a desired impedance between the collector of the third transistor and the power supply terminal while matching that impedance to the impedance of a lead connected to the output terminal.

Claim 3

A circuit as recited in claim 1, further comprising means in the form of a low pass network connected between the second common node and the second resistor for increasing the RF impedance without affecting DC bias.

Claim 4

A circuit as recited in claim 2, wherein the low pass network includes an inductor connected between the second common node and the second resistor and a capacitor connected between the common ground and node common to the inductor and the second resistor.

Claim 5

A circuit as recited in claim 1, further comprising means in the form of a capacitor connected between the first common node and the input terminal for blocking DC while presenting a low impedance RF path.

Claim 6

A circuit as recited in claim 1, further comprising means in the form of a current source connected between the second common node and the third resistor for setting the bias for a selected one of class A, class AB, and class B operation.

Claim 7

A circuit as recited in claim 5, wherein the current source includes: fourth and fifth transistors and fourth and fifth resistors, each of the fourth and fifth transistors having a base, an emitter, and a collector; the fourth transistor having its collector connected to the second common node, its emitter connected to the third resistor, and its base connected to a third common node; the fifth transistor having its base and its collector connected to the third common node; the fourth resistor being connected between the emitter of the fifth transistor and the common ground; and the fifth resistor being connected between the third common node and a second control node.

Claim 8

A circuit as recited in claim 6, wherein the input terminal is connected to the third common node.

Claim 9

A circuit as recited in claim 1, wherein the input terminal is connected to the first common node.

Claim 10

An amplifier circuit having an input terminal, an output terminal, a power supply terminal, and a control node, the amplifier circuit comprising: means in the form of first, second, and third field effect transistors interconnected in a modified current source configuration with first, second, and third resistors and a matching circuit for producing a desired bias current according to the magnitude of a control voltage coupled to the control node while producing an amplified output radio frequency signal at the output terminal from an input radio frequency signal coupled to the input terminal, each of the first, second, and third field effect transistors having a gate, a source, and a drain; the first transistor having its drain connected to a first common node, its gate connected to a second common node, and its source connected to a common ground; the second transistor having its gate connected to the first common node and its drain connected to the power supply terminal; the third transistor having its gate connected to the second common node and its source connected to the common ground; the first resistor being connected between the first common node and the control node; the second resistor being connected between the source of the second transistor and the second common node; the third resistor being connected between the second common node and the common ground; and the matching circuit including means connected to the drain of the third transistor, the power supply terminal, and the output terminal for presenting a desired impedance between the drain of the third transistor and the power supply terminal and for matching that impedance to the impedance of a load connected to the output terminal.

Claim 11

An amplifier circuit having an input terminal, an output terminal, a power supply terminal, and a control node, the amplifier circuit comprising: means in the form of first, second, and third field effect transistors interconnected in a modified current source configuration with first, second, and third resistors and a matching circuit for producing a desired bias current according to the magnitude of a control voltage coupled to the control node while producing an amplified output radio frequency signal at the output terminal from an input radio frequency signal coupled to the input terminal, each of the first, second, and third field effect transistors having a gate, a source, and a drain; the first transistor having its drain connected to a first common node, its gate connected to a second common node, and its source connected to a common ground; the second transistor having its gate connected to the first common node and its drain connected to the power supply terminal; the third transistor having its gate connected to the second common node and its source connected to the common ground; the first resistor being connected between the first common node and the control node; the second resistor being connected between the source of the second transistor and the second common node; the third resistor being connected between the second common node and the common ground; and the matching circuit including means connected to the drain of the third transistor, the power supply terminal, and the output terminal for presenting a desired impedance between the drain of the third transistor and the power supply terminal and for matching that impedance to the impedance of a load connected to the output terminal.

Claim 12

A circuit as recited in claim 9, further comprising means in the form of a low pass network connected between the second common node and the second resistor for increasing RF impedance without affecting DC bias.

Claim 13

A circuit as recited in claim 10, wherein the low pass network includes an inductor connected between the second common node and the second resistor and a capacitor connected between the common ground and node common to the inductor and the second resistor.

Claim 14

A circuit as recited in claim 9, further comprising means in the form of a capacitor connected between the first common node and the input terminal for blocking DC while presenting a low impedance RF path.

Claim 15

A circuit as recited in claim 9, further comprising means in the form of a current source connected between the second common node and the third resistor for setting the bias for a selected one of class A, class AB, and class B operation.

Claim 16

A circuit as recited in claim 13, wherein the current source includes: fourth and fifth field effect transistors and fourth and fifth resistors, each of the fourth and fifth transistors having a gate, a source, and a drain; the fourth transistor having its drain connected to the second common node, its source connected to the third resistor, and its gate connected to a third common node; the fifth transistor having its gate connected to the third common node and its drain connected to the third common node; the fourth resistor connected between the source of the fifth transistor and the common ground; and the fifth resistor connected between the third common node and a second control node.

Claim 17

An amplifier circuit having an input terminal, an output terminal, a power supply terminal, and a control node, the amplifier circuit comprising: means in the form of first, second, third, and fourth field effect transistors interconnected in a modified current source configuration with first, second, third, and fourth resistors, a diode combination, and a matching circuit for producing a desired bias current according to the magnitude of a control voltage coupled to the control node while producing an amplified output radio frequency signal at the output terminal from an input radio frequency signal coupled to the input terminal, each of the first, second, third, and fourth transistors having a gate, a source, and a drain; the first transistor having its gate connected to a first common node, its source connected to a common ground, and its drain connected to a third common node; the second transistor having its source connected to the common ground; the third transistor having its source connected to the common ground and its drain connected to the third common node; the fourth transistor having both its gate and its source connected to the third common node and its drain connected to the power supply terminal; the first resistor being connected between the second common node and the gate of the first transistor; the second resistor being connected between the second common node and the gate of the second transistor; the third resistor being connected between the second common node and the gate of the first transistor; the fourth resistor being connected between the second common node and the control node; and the diode combination being connected between the second common node the third common node.

Claim 18

An amplifier circuit having an input terminal, an output terminal, a power supply terminal, and a control node, the amplifier circuit comprising: means in the form of first, second, third, and fourth field effect transistors interconnected in a modified current source configuration with first, second, third, and fourth resistors, a diode combination, and a matching circuit for producing a desired bias current according to the magnitude of a control voltage coupled to the control node while producing an amplified output radio frequency signal at the output terminal from an input radio frequency signal coupled to the input terminal, each of the first, second, third, and fourth transistors having a gate, a source, and a drain; the first transistor having its gate connected to a first common node, its source connected to a common ground, and its drain connected to a third common node; the second transistor having its source connected to the common ground; the third transistor having its source connected to the common ground and its drain connected to the third common node; the fourth transistor having both its gate and its source connected to the third common node and its drain connected to the power supply terminal; the first resistor being connected between the second common node and the gate of the first transistor; the second resistor being connected between the second common node and the gate of the second transistor; the third resistor being connected between the second common node and the gate of the first transistor; the fourth resistor being connected between the second common node and the control node; and the diode combination being connected between the second common node the third common node.