← Back to Patent Explorer
US6514809B1 Expired / Lapsed US ⏱️ 0.0 years remaining

SOI field effect transistors with body contacts formed by selective etch and fill

Assignee: Advanced Micro Devices Inc
•
Filing: 2000-11-03
•
Granted: 2003-02-04
•
Expires: 2020-11-03
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A field effect transistor on an SOI wafer has a non-floating body which is tied to the substrate of the wafer by a bridge of conductive material such as semiconductor material. The bridge is created by selectively etching through a portion of a surface semiconductor layer and the underlying portion of a buried insulator layer, thereby making an opening or trench which exposing some of the semiconductor substrate of the SOI wafer. Then the opening is filled, for example by growth of a replacement semiconductor material by selective epitaxy.

Inventors

  • 👤 Qi Xiang

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 08:27
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/6704; H10D30/6708; H10D30/6758

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 142 words
A method of forming a semiconductor device, comprising: forming a dummy gate on an active region of a surface semiconductor layer which is separated from a semiconductor substrate by an intervening buried insulator layer; selectively doping portions of the active region to form a source and a drain on opposite sides of a body, using the dummy gate as a doping mask; removing the dummy gate; exposing a portion of the semiconductor substrate by removing overlying portions of the active layer and of the buried insulator layer, thereby forming an opening perforating the surface semiconductor layer and the buried insulator layer, wherein the exposing includes etching the active region and the insulating layer through a space left by removal of the dummy gate; and epitaxially growing a semiconductor material to fill the opening and thereby electrically connect the substrate and the body.
Claim 2
Independent Claim 142 words
A method of forming a semiconductor device, comprising: forming a dummy gate on an active region of a surface semiconductor layer which is separated from a semiconductor substrate by an intervening buried insulator layer; selectively doping portions of the active region to form a source and a drain on opposite sides of a body, using the dummy gate as a doping mask; removing the dummy gate; exposing a portion of the semiconductor substrate by removing overlying portions of the active layer and of the buried insulator layer, thereby forming an opening perforating the surface semiconductor layer and the buried insulator layer, wherein the exposing includes etching the active region and the insulating layer through a space left by removal of the dummy gate; and epitaxially growing a semiconductor material to fill the opening and thereby electrically connect the substrate and the body.
Claim 3
Dependent Claim 25 words
The method of claim 1 , wherein the semiconductor material includes doped semiconductor material, and wherein the epitaxially growing includes growing the doped semiconductor material.
Claim 4
Dependent Claim 42 words
The method of claim 1 , wherein the expitaxially growing includes forming a semiconductor material bridge electrically connecting the substrate and the body; and wherein a cross-sectional area of the semiconductor material bridge is smaller than a cross-sectional area of the body.
Claim 5
Dependent Claim 22 words
The method of claim 3 , wherein the source and the drain are electrically-isolated from the substrate by the buried insulator layer.
Claim 6
Dependent Claim 27 words
The method of claim 1 , wherein the epitaxially growing includes forming a semiconductor material bridge electrically connecting the substrate and a central portion of the body.
Claim 7
Dependent Claim 26 words
The method of claim 1 , wherein the epitaxially growing includes forming a semiconductor material bridge electrically connecting the substrate and an underside of the body.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2006-02-03 2006-08-05 2007-02-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2010-02-03 2010-08-05 2011-02-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2014-02-03 2014-08-05 2015-02-04 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag