Patent US6509221B1 successfully refreshed from Google Patents.
US6509221B1
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US
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Method for forming high performance CMOS devices with elevated sidewall spacers
Assignee: GlobalFoundries US Inc
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Filing: 2001-11-15
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Granted: 2003-01-21
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Expires: 2021-11-15
Abstract
Abstract A method is described for making elevated sidewall spacers on the gate structure of a semiconductor device. A first insulating layer is deposited on the substrate, so that an upper portion of each of the sidewalls extends above the layer. A second insulating layer is deposited on the first layer and on the gate structure. Portions of the second layer disposed on the first layer and on the top surface of the gate structure are removed, so that a remaining portion of the second layer is disposed on the upper portion of each of the sidewalls. The first layer is then removed, so that the remaining portion of the second layer on each of the sidewalls projects laterally therefrom and is elevated with respect to the substrate. This structure is used to implant PFET and NFET extension regions without dose loss.
Inventors
- 👤 Bruce B. Doris
- 👤 Omer H. Dokumaci
- 👤 Oleg Gluschenkov
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:39
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0184; H10D84/02; H10D84/03; H10D84/038; H10P; H10P30/00; H10P30/20; H10P30/22; H10P30/221; H10P30/222
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
142 words
A method for making a semiconductor device having an NFET device and a PFET device, each of the NFET device and the PFET device including a gate structure on a substrate, the gate structure having a top surface and sidewalls, the method comprising the steps of: forming a spacer disposed on each of the sidewalls and projecting laterally therefrom, the spacer covering an upper portion of the sidewall and being elevated with respect to the substrate; performing a first ion implantation at an angle of incidence other than normal to the substrate, thereby forming an implanted region in the substrate adjacent to the NFET gate structure, and performing a second ion implantation at normal incidence to the substrate, thereby forming an implanted region in the substrate offset from the PFET gate structure in accordance with a lateral projection distance of the spacer.
Claim 2
Independent Claim
142 words
A method for making a semiconductor device having an NFET device and a PFET device, each of the NFET device and the PFET device including a gate structure on a substrate, the gate structure having a top surface and sidewalls, the method comprising the steps of: forming a spacer disposed on each of the sidewalls and projecting laterally therefrom, the spacer covering an upper portion of the sidewall and being elevated with respect to the substrate; performing a first ion implantation at an angle of incidence other than normal to the substrate, thereby forming an implanted region in the substrate adjacent to the NFET gate structure, and performing a second ion implantation at normal incidence to the substrate, thereby forming an implanted region in the substrate offset from the PFET gate structure in accordance with a lateral projection distance of the spacer.
Claim 3
Dependent Claim
117 words
The method of claim 1 , wherein said step of forming a spacer comprises: forming a first layer on the substrate; depositing a second layer on the first layer and on the gate structure; removing portions of the second layer disposed on the first layer and on the top surface of the gate structure, so that a remaining portion of the second layer is disposed on the upper portion of each of the sidewalls; and removing the first layer, so that the remaining portion of the second layer on each of the sidewalls projects laterally therefrom and is elevated with respect to the substrate, the lateral projection distance being determined by a thickness of the second layer.
Claim 4
Dependent Claim
21 words
The method of claim 2 , wherein said step of removing portions of the second layer comprises a directional etching process.
Claim 5
Dependent Claim
46 words
The method of claim 2 , wherein said step of forming the first layer comprises: depositing the first layer on the substrate; and removing a top portion of the first layer, so that an upper portion of each of the sidewalls extends above the first layer.
Claim 6
Dependent Claim
23 words
The method of claim 4 , wherein said step of removing a top portion of the first layer comprises a non-directional etching process.
Claim 7
Dependent Claim
18 words
The method of claim 2 , wherein the first layer and the second layer are of insulating materials.
Claim 8
Dependent Claim
76 words
The method of claim 1 , wherein the substrate includes an NFET device area and a PFET device areas, said step of performing the first ion implantation further comprises masking the substrate so that the NFET device area is exposed and the PFET device area is masked, and said step of performing the second ion implantation further comprises masking the substrate so that the PFET device area is exposed and the NFET device area is masked.
Claim 9
Dependent Claim
33 words
The method of claim 1 , further comprising the step of forming an oxide layer on the substrate and on the sidewalls of the gate structure, before said step of forming a spacer.
Claim 10
Dependent Claim
44 words
The method of claim 8 , wherein the oxide layer has a thickness not greater than 10 nm, and the first ion implantation process forms an implanted region in the substrate offset from the NFET gate structure in accordance with said oxide layer thickness.
Claim 11
Dependent Claim
27 words
The method of claim 1 , wherein the first ion implantation process is performed using ions selected from the group consisting of As, P and Sb ions.
Claim 12
Dependent Claim
58 words
The method of claim 1 , further comprising the step of performing an additional ion implantation after the first ion implantation, said additional ion implantation being performed at normal incidence to the substrate, thereby forming an additional implanted region in the substrate offset from the NFET gate structure in accordance with the lateral projection distance of the spacer.
Claim 13
Dependent Claim
24 words
The method of claim 1 , wherein the first ion implantation is performed with an implantation dose greater than 1×10 14 atoms/cm 2 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-01-20 | 2006-07-22 | 2007-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-01-20 | 2010-07-22 | 2011-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-01-20 | 2014-07-22 | 2015-01-21 | $7700.00 | Window Closed / Lapsed |