US6501300B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit
Assignee: Renesas Electronics Corp
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Filing: 2001-07-10
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Granted: 2002-12-31
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Expires: 2021-07-10
Abstract
Abstract The present invention includes a logic circuit block operated in synchronism with a clock signal, power supply switches, and a power supply switch control circuit for switch-controlling the power supply switches so as to provide an operation period shorter than the cycle of the clock signal. When the logic circuit block activated in synchronism with a clock signal has a frequency lower than a clock signal frequency, the logic circuit block does not develop a malfunction if capable of operation for each cycle of the clock signal at least only for a time interval defined by the clock signal frequency of the maximum operation speed. Since the supplying of operating power to the logic circuit block is cut off according to the clock signal frequency except for a period necessary for a circuit operation, leak current, that will flow through each turned-off transistor in the meantime, can be significantly reduced.
Inventors
- 👤 Hiroshi Hatae
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:28
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0016
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
262 words
A data processing system, comprising: a plurality of logic circuit blocks operated in synchronism with a clock signal supplied thereto; a clock control circuit which controls the supply of the clock signal to said plurality of logic circuit blocks; at least one power supply switch which controls the supply of a power supply to said plurality of logic circuit blocks; and a switch control circuit which controls the turning on and off of said power supply switch, wherein said clock control circuit supplies a first clock signal to said plurality of logic circuit blocks in response to the designation of a low-speed mode, supplies a second clock signal higher than the first clock signal in frequency to said plurality of logic circuit blocks in response to the designation of a high-speed mode, and stops the supply of the clock signal to a predetermined logic circuit block of said plurality of logic blocks in response to the designation of a standby mode, and wherein said switch control circuit controls said power supply switch in response to the designation of the low-speed mode so as to bring a period shorter than the cycle of the first clock signal to an on operation period in synchronism with the first clock signal, controls said power supply switch to an on state at all times in response to the designation of the high-speed mode, and turns on said power supply switch for each predetermined period in response to the designation of the standby mode, thereby refreshing potentials at internal nodes in said plurality of logic circuit blocks.
Claim 2
Dependent Claim
262 words
A data processing system, comprising: a plurality of logic circuit blocks operated in synchronism with a clock signal supplied thereto; a clock control circuit which controls the supply of the clock signal to said plurality of logic circuit blocks; at least one power supply switch which controls the supply of a power supply to said plurality of logic circuit blocks; and a switch control circuit which controls the turning on and off of said power supply switch, wherein said clock control circuit supplies a first clock signal to said plurality of logic circuit blocks in response to the designation of a low-speed mode, supplies a second clock signal higher than the first clock signal in frequency to said plurality of logic circuit blocks in response to the designation of a high-speed mode, and stops the supply of the clock signal to a predetermined logic circuit block of said plurality of logic blocks in response to the designation of a standby mode, and wherein said switch control circuit controls said power supply switch in response to the designation of the low-speed mode so as to bring a period shorter than the cycle of the first clock signal to an on operation period in synchronism with the first clock signal, controls said power supply switch to an on state at all times in response to the designation of the high-speed mode, and turns on said power supply switch for each predetermined period in response to the designation of the standby mode, thereby refreshing potentials at internal nodes in said plurality of logic circuit blocks.
Claim 3
Dependent Claim
256 words
A data processing system, comprising: a plurality of logic circuit blocks operated in synchronism with a clock signal supplied thereto; a clock control circuit which controls the supply of the clock signal to said plurality of logic circuit blocks; at least one power supply switch which controls the supply of a power supply to said plurality of logic circuit blocks; and a switch control circuit which controls the turning on and off of said power supply switch, wherein said clock control circuit supplies a first clock signal to said plurality of logic circuit blocks in response to the designation of a low-speed mode, supplies a second clock signal higher than the first clock signal in frequency to said plurality of logic circuit blocks in response to the designation of a high-speed mode, and stops the supply of the clock signal to a predetermined logic circuit block of said plurality of logic blocks in response to the designation of a standby mode, and wherein said switch control circuit switch-controls said power supply switch in response to the designation of the low-speed mode so as to bring a period shorter than the cycle of the first clock signal to an on operation period in synchronism with the first clock signal, controls said power supply switch to an on state at all times in response to the designation of the high-speed mode, and controls the power supply switch of said predetermined logic block to an off state at all times in response to the designation of the standby mode.
Claim 4
Dependent Claim
256 words
A data processing system, comprising: a plurality of logic circuit blocks operated in synchronism with a clock signal supplied thereto; a clock control circuit which controls the supply of the clock signal to said plurality of logic circuit blocks; at least one power supply switch which controls the supply of a power supply to said plurality of logic circuit blocks; and a switch control circuit which controls the turning on and off of said power supply switch, wherein said clock control circuit supplies a first clock signal to said plurality of logic circuit blocks in response to the designation of a low-speed mode, supplies a second clock signal higher than the first clock signal in frequency to said plurality of logic circuit blocks in response to the designation of a high-speed mode, and stops the supply of the clock signal to a predetermined logic circuit block of said plurality of logic blocks in response to the designation of a standby mode, and wherein said switch control circuit switch-controls said power supply switch in response to the designation of the low-speed mode so as to bring a period shorter than the cycle of the first clock signal to an on operation period in synchronism with the first clock signal, controls said power supply switch to an on state at all times in response to the designation of the high-speed mode, and controls the power supply switch of said predetermined logic block to an off state at all times in response to the designation of the standby mode.
Claim 5
Dependent Claim
62 words
The data processing system as claimed in claim 1 , wherein said plurality of logic circuit blocks respectively constitute processors and said each processor includes a CPU subjected to clock control and power-supply control responsive to the high-speed, low-speed and standby modes, and an interrupt control circuit subjected to the clock control and power-supply control responsive to the high-speed and low-speed modes.
Claim 6
Dependent Claim
64 words
The data processing system as claimed in claim 3 , wherein said power control circuit resumes the supply of a power supply to said plurality of logic circuit blocks in response to a standby mode reset signal, and said clock control circuit resumes the supply of a clock signal to said plurality of logic circuit blocks in response to the standby mode reset signal.
Claim 7
Dependent Claim
27 words
The data processing system as claimed in claim 4 , further including display means, input means and communication means placed under the control of said each processor.
Claim 8
Dependent Claim
230 words
A semiconductor integrated circuit, comprising: a first terminal supplied with a first operation potential; a second terminal supplied with a second operation potential different from the first operation potential; a logic circuit block having a data input node, a data output node, first and second power supply nodes, and a clock input node; a fist switching element connected between said first terminal and the first power supply node; a second switching element connected between said second terminal and the second power supply node; a mode setting circuit which stores therein mode information for defining one operation mode specified out of a first operation mode for specifying the supply of a first operating clock to the clock input node and a second operation mode for specifying the supply of a second operating clock having a frequency higher than the frequency of the first operating clock to the clock input node; a clock control circuit which controls the supply of the first and second operating clocks to the clock input node in response to a signal outputted from said mode setting circuit; and a switching control circuit which selectively controls said first and second switching elements to an operating state in response to the setting of the first operation mode and controls said first and second switching elements to an operating state in response to the setting of the second operation mode.
Claim 9
Dependent Claim
230 words
A semiconductor integrated circuit, comprising: a first terminal supplied with a first operation potential; a second terminal supplied with a second operation potential different from the first operation potential; a logic circuit block having a data input node, a data output node, first and second power supply nodes, and a clock input node; a fist switching element connected between said first terminal and the first power supply node; a second switching element connected between said second terminal and the second power supply node; a mode setting circuit which stores therein mode information for defining one operation mode specified out of a first operation mode for specifying the supply of a first operating clock to the clock input node and a second operation mode for specifying the supply of a second operating clock having a frequency higher than the frequency of the first operating clock to the clock input node; a clock control circuit which controls the supply of the first and second operating clocks to the clock input node in response to a signal outputted from said mode setting circuit; and a switching control circuit which selectively controls said first and second switching elements to an operating state in response to the setting of the first operation mode and controls said first and second switching elements to an operating state in response to the setting of the second operation mode.
Claim 10
Dependent Claim
65 words
The semiconductor integrated circuit as claimed in claim 6 , wherein said each logic circuit block includes, a combinational circuit connected to the data input, node; and a flip-flop circuit which latches a signal outputted from said combinational circuit therein in response to a change of the clock signal supplied to the clock input node from a first level thereof to a second level thereof.
Claim 11
Dependent Claim
74 words
The semiconductor integrated circuit as claimed in claim 7 , wherein said mode setting circuit is further capable of setting a third operation mode for specifying the cutting off of the supply of the first and second clocks to the clock input node, and said switching control circuit controls said first and second switching elements to a non-operating state in response to the setting of the third operation mode to said mode setting circuit.
Claim 12
Dependent Claim
38 words
The semiconductor integrated circuit as claimed in claim 6 , wherein said logic circuit block comprises a plurality of PMOS transistors and NMOS transistors, and said first and second switching elements respectively include PMOS transistors and NMOS transistors.
Claim 13
Dependent Claim
47 words
The semiconductor integrated circuit as claimed in claim 9 , wherein threshold voltages of the PMOS transistors and the NMOS transistors of said logic circuit block are respectively lower than threshold voltages of the PMOS transistors and the NMOS transistors of said first and second switching elements.
Claim 14
Dependent Claim
57 words
The semiconductor integrated circuit as claimed in claim 6 , wherein said switching control circuit responds to the setting of the first operation mode and selectively controls said first and second switching elements to an operating state for each cycle of the first operating clock during a period corresponding to one cycle of the second operating clock.
Claim 15
Dependent Claim
220 words
A semiconductor integrated circuit, comprising: a first terminal supplied with a first operation potential; a second terminal supplied with a second operation potential different from the first operation potential; a logic circuit block having a data input node, a data output node, first and second power supply nodes, and a clock input node; a switching element connected between said first terminal and the first power supply node or between said second terminal and the second power supply node; a mode setting circuit which stores therein mode information for defining one operation mode specified out of a first operation mode for specifying the supply of a first operating clock to the clock input node and a second operation mode for specifying the supply of a second operating clock having a frequency higher than the frequency of the first operating clock to the clock input node; a clock control circuit which responds to a signal outputted from said mode setting circuit and thereby controls the supply of the first and second operating clocks to the clock input node; and a switching control circuit which selectively controls said switching element to an operating state in response to the setting of the first operation mode and controls said switching element to an operating state in response to the setting of the second operation mode.
Claim 16
Dependent Claim
220 words
A semiconductor integrated circuit, comprising: a first terminal supplied with a first operation potential; a second terminal supplied with a second operation potential different from the first operation potential; a logic circuit block having a data input node, a data output node, first and second power supply nodes, and a clock input node; a switching element connected between said first terminal and the first power supply node or between said second terminal and the second power supply node; a mode setting circuit which stores therein mode information for defining one operation mode specified out of a first operation mode for specifying the supply of a first operating clock to the clock input node and a second operation mode for specifying the supply of a second operating clock having a frequency higher than the frequency of the first operating clock to the clock input node; a clock control circuit which responds to a signal outputted from said mode setting circuit and thereby controls the supply of the first and second operating clocks to the clock input node; and a switching control circuit which selectively controls said switching element to an operating state in response to the setting of the first operation mode and controls said switching element to an operating state in response to the setting of the second operation mode.
Claim 17
Dependent Claim
64 words
The semiconductor integrated circuit as claimed in claim 12 , wherein said logic circuit block includes, a combinational circuit connected to the data input node; and a flip-flop circuit which latches a signal outputted from said combinational circuit therein in response to a change of the clock signal supplied to the clock input node from a first level thereof to a second level thereof.
Claim 18
Dependent Claim
62 words
The data processing system as claimed in claim 13 , wherein said plurality of logic circuit blocks respectively constitute processors and said each processor includes a CPU subjected to clock control and power-supply control responsive to the high-speed, low-speed and standby modes, and an interrupt control circuit subjected to the clock control and power-supply control responsive to the high-speed and low-speed modes.
Claim 19
Dependent Claim
64 words
The data processing system as claimed in claim 14 , wherein said power control circuit resumes the supply of a power supply to said plurality of logic circuit blocks in response to a standby mode reset signal, and said clock control circuit resumes the supply of a clock signal to said plurality of logic circuit blocks in response to the standby mode reset signal.
Claim 20
Dependent Claim
27 words
The data processing system as claimed in claim 15 , further including display means, input means and communication means placed under the control of said each processor.
Claim 21
Dependent Claim
71 words
The semiconductor integrated circuit as claimed in claim 12 , wherein said mode setting circuit is further capable of setting a third operation mode for specifying the cutting off of the supply of the first and second clocks to the clock input node, and said switching control circuit controls said switching element to a non-operating state in response to the setting of the third operation mode to said mode setting circuit.
Claim 22
Dependent Claim
38 words
The semiconductor integrated circuit as claimed in claim 12 , wherein said logic circuit block comprises MOS transistors, and said switching element includes MOS transistors lower than the MOS transistors of said logic circuit block in threshold voltage.
Claim 23
Dependent Claim
54 words
The semiconductor integrated circuit as claimed in claim 12 , wherein said switching control circuit responds to the setting of the first operation mode and selectively controls said switching element to an operating state for each cycle of the first operating clock during a period corresponding to one cycle of the second operating clock.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-12-30 | 2006-07-01 | 2006-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-12-30 | 2010-07-01 | 2010-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-12-30 | 2014-07-01 | 2014-12-31 | $7700.00 | Window Closed / Lapsed |