Semiconductor integrated circuit having a sleep mode with low power and small area

Claim 1

A semiconductor integrated circuit comprising: a power source circuit having only three source lines, said power source circuit including a first global source line, a local source line coupled to said first global source line by a source switching transistor and a second global source line; a low threshold logic circuit connected between said local source line and said second global source line, said low-threshold logic circuit including an output stage; a data storage circuit connected between said first global source line and said second global source line, said data storage circuit including a low-threshold input section for receiving a data signal from said output stage and a high-threshold latch section for latching the data signal received by said input section, said power source circuit further including a first mode switching transistor for coupling said output stage and said second global source line, a second mode switching transistor for coupling said input section and said first global source line, and a third mode switching transistor for coupling said input section and said second source line, each of said first through third switching transistors and said source switching transistor being controlled by a mode signal for supplying power from said first and second global source lines.