US5606265A
Expired / Lapsed
US
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Semiconductor integrated circuits with power reduction mechanism
Assignee: PS4 Luxco SARL
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Filing: 1996-03-21
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Granted: 1997-02-25
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Expires: 2016-03-21
Abstract
Abstract This invention is to reduce the power dissipation of a semiconductor integrated circuit chip when it is operated at an operating voltage of 2.5 V or below. To achieve the object, a switching element is provided in each circuit block within the semiconductor integrated circuit chip. The constants of the switching element are set so that the leak current in the switching element of each circuit block in their off-state is smaller than the subthreshold current of the MOS transistors within the corresponding circuit block. The active current is supplied to the active circuit blocks, while the switching elements of the non-active circuit blocks are turned off. Thus, the dissipation currents of the non-active circuit blocks are limited to the leak current value of the corresponding switching elements. As a result, the sum of the dissipation currents of the non-active circuit blocks is made smaller than the active current in the active circuit blocks. Since the dissipation currents of the non-active circuit blocks can be reduced while the active current is caused to flow in the active circuit blocks, the power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.
Inventors
- 👤 Takeshi Sakata
- 👤 Kiyoo Itoh
- 👤 Masashi Horiguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:12
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0016; G; G11; G11C; G11C5/00; G11C5/14; G11C5/147; G11C7/00; G11C7/06; G11C7/065; G11C7/08; G11C8/00; G11C8/08; G11C8/12; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
323 words
A semiconductor integrated circuit comprising: a plurality of column lines; a plurality of row lines; a plurality of memory cells disposed at desired intersections between said column lines and said row lines; and a selection circuit for selecting said memory cells comprising: a first node and a second node supplied with a first operating voltage; a third node and a fourth node supplied with second operating voltage; a plurality of first logic gates connected between said first node and said third node; a plurality of second logic gates connected between said second node and said fourth node; first current controlling means provided between said first logic gates and said first node; and second current controlling means provided between said second logic gates and said fourth node, wherein respective outputs of said first logic gates are connected to respective inputs of said second logic gates, wherein, in a first condition, a first current path is formed between said first node and an output of at least one of said first logic gates through said first current control means, and a second current path is formed between said fourth node and an output of at least one of said second logic gates through said second current control means, and wherein, in a second condition, a third current path is formed between said third node and outputs of said first logic gates, respectively, and a fourth current path is formed between said second node and outputs of said second logic gates, respectively, and a first current capacity flowing between said first node and said first logic gates in said second condition is set smaller than said first current capacity in said first condition by said first current control means, and a second current capacity flowing between said fourth node and said second logic gates in said second condition is set smaller than said second current capacity in said first condition by said second current control means.
Claim 2
Dependent Claim
323 words
A semiconductor integrated circuit comprising: a plurality of column lines; a plurality of row lines; a plurality of memory cells disposed at desired intersections between said column lines and said row lines; and a selection circuit for selecting said memory cells comprising: a first node and a second node supplied with a first operating voltage; a third node and a fourth node supplied with second operating voltage; a plurality of first logic gates connected between said first node and said third node; a plurality of second logic gates connected between said second node and said fourth node; first current controlling means provided between said first logic gates and said first node; and second current controlling means provided between said second logic gates and said fourth node, wherein respective outputs of said first logic gates are connected to respective inputs of said second logic gates, wherein, in a first condition, a first current path is formed between said first node and an output of at least one of said first logic gates through said first current control means, and a second current path is formed between said fourth node and an output of at least one of said second logic gates through said second current control means, and wherein, in a second condition, a third current path is formed between said third node and outputs of said first logic gates, respectively, and a fourth current path is formed between said second node and outputs of said second logic gates, respectively, and a first current capacity flowing between said first node and said first logic gates in said second condition is set smaller than said first current capacity in said first condition by said first current control means, and a second current capacity flowing between said fourth node and said second logic gates in said second condition is set smaller than said second current capacity in said first condition by said second current control means.
Claim 3
Dependent Claim
297 words
A semiconductor integrated circuit according to claim 1, further comprising: a plurality of third logic gates connected between said first node and said third node; a plurality of fourth logic gates connected between said second node and said fourth node; third current control means provided between said first node and said third logic gates; and fourth current control means provided between said fourth node and said fourth logic gates, wherein respective outputs of said third logic gates are connected to said respective inputs of said fourth logic gates, wherein, in a third condition, a fifth current path is formed between said first node and an output of at least one of said third logic gates through said third current control means, and a sixth current path is formed between said fourth node and an output of at least one of said fourth logic gates through said fourth current control means, wherein, in a fourth condition, a seventh current path is formed between said third node and respective outputs of said third logic gates, and an eighth current path is formed between said second node and respective outputs of said fourth logic gates, and a third current capacity flowing between said first gate and said third logic gates in said fourth condition is set smaller than said third current capacity in said third condition by said third current control means, and a fourth current capacity flowing between said fourth node and said fourth logic gates in said fourth condition is set smaller than said fourth current capacity in said third condition by said fourth current control means, and wherein said third logic gates and said fourth logic gates are in said fourth condition when said first logic gates and said second logic gates are in said third condition.
Claim 4
Dependent Claim
121 words
A semiconductor integrated circuit according to claim 2, further comprising: a first power source line through which said first operating voltage is supplied to said first node; a second power source line through which said second operating voltage is supplied to said first node; first main current control means provided between said first power source line and said first node; and second main current control means provided between said second power source line and said fourth node, wherein, in said first condition or said third condition, said first operating voltage is supplied to said first node through said first main current control means, and said second operating voltage is supplied to said fourth node through said second main current control means.
Claim 5
Dependent Claim
126 words
A semiconductor integrated circuit according to claim 3, further comprising: a fifth node and a sixth node supplied with a first operating voltage; a seventh node and an eighth node supplied with a second operating voltage; a plurality of fifth logic gates connected between said fifth node and said seventh node; a plurality of sixth logic gates connected between said sixth node and said eighth node; fifth current control means provided between said fifth node and said fifth logic gates; sixth current control means provided between said eighth node and said-sixth logic gates; third main current control means provided between said first power source line and said fifth node; and fourth main current control means provided between said second power source line and said eighth node.
Claim 6
Dependent Claim
73 words
A semiconductor integrated circuit according to claim 1, wherein said first current control means includes a first MOS transistor having a source which is connected to said first node and a drain which is connected to said first logic gates, and wherein said second current control means includes a second MOS transistor having a source which is connected to said fourth node and a drain which is connected to said second logic gates.
Claim 7
Dependent Claim
92 words
A semiconductor integrated circuit according to claim 5, wherein both absolute values of threshold voltages of said first MOS transistor and said second MOS transistor are larger than absolute values of threshold voltages of MOS transistors included in said first logic gates and said second logic gates, wherein the threshold voltages are each defined as a constant threshold voltage measured between a gate and a source in a condition of an absolute drain current value of 10 nA, a ratio of effective gate width/effective gate length of 30, and a room temperature.
Claim 8
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 5, wherein polarities of said first MOS transistor and said second MOS transistor are complementary to each other.
Claim 9
Dependent Claim
25 words
A semiconductor integrated circuit according to claim 1, wherein said first logic gates and said second logic gates are formed by CMOS logic gates, respectively.
Claim 10
Dependent Claim
17 words
A semiconductor integrated circuit according to claim 8, wherein said first logic gates are formed by multi-inputs-outputs.
Claim 11
Dependent Claim
18 words
A semiconductor integrated circuit according to claim 9, wherein said first logic gates are formed by NAND gates.
Claim 12
Dependent Claim
17 words
A semiconductor integrated circuit according to claim 8, wherein said second logic gates are formed by inverters.
Claim 13
Dependent Claim
20 words
A semiconductor integrated circuit according to claim 1, wherein storage capacities of said memory cells are more than 16 Gbits.
Claim 14
Dependent Claim
77 words
A semiconductor integrated circuit according to claim 1, wherein both said first logic gates and said second logic gates include a transistor having a gate voltage which varies from a first voltage to a second voltage, and a drain current which becomes larger in said second voltage than in said first voltage, and having a penetrating current which substantially flows between a drain and a source even if said gate voltage is equal to said first voltage.
Claim 15
Dependent Claim
39 words
A semiconductor integrated circuit according to claim 13, wherein substrates of said MOS transistors included in said first logic gates and said second logic gates, respectively, are applied with a fixed constant voltage equal to said second operating voltage.
Claim 16
Dependent Claim
81 words
A semiconductor integrated circuit according to claim 13, wherein respective threshold voltages of said MOS transistors of said first logic gates and said second logic gates are equal to or less than 0.2 V, where the threshold voltages are each defined as a threshold voltage of a constant current measured between a gate and a source in a condition of an absolute drain current of 10 nA, absolute ratio of effective gate width/effective gate length of 30, and a room temperature.
Claim 17
Dependent Claim
36 words
A semiconductor integrated circuit according to claim 13, wherein thicknesses of gate oxide films of said MOS transistors of said first logic gates and said second logic gates are equal to or less than 6 nm.
Claim 18
Dependent Claim
34 words
A semiconductor integrated circuit according to claim 13, wherein effective channel lengths of said MOS transistors of said first logic gates and said second logic gates are equal to or less than 0.25 μm.
Claim 19
Dependent Claim
32 words
A semiconductor integrated circuit according to claim 1, wherein an absolute value of an electric source voltage applied from outside said semiconductor integrated circuit is equal to or less than 2.5 V.
Claim 20
Dependent Claim
27 words
A semiconductor integrated circuit according to claim 1, wherein a difference between said first voltage and said second voltage is equal to or less than 2.5 V.
References Cited (Backward Citations)
US4209713A
Cited
US5197033A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-02-25 | 2000-08-26 | 2001-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-02-25 | 2004-08-26 | 2005-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-02-25 | 2008-08-26 | 2009-02-25 | $7700.00 | Window Closed / Lapsed |