CMOS logic circuits having low and high-threshold voltage transistors

Claim 2

A circuit comprising: a logic circuit having a plurality of logic circuit elements each comprised of a plurality of field effect transistors; first and second power lines for supplying power to said logic, with said first power line connected to a power source and with said second power line connected to a ground; a first dummy power line connected to one of a plurality of power source terminals of said logic circuit; and a first control transistor connected between said first dummy power line and said first power line, said first control transistor having a threshold substantially greater than thresholds of said field effect transistors of said logic circuit.

Claim 3

A circuit according to claim 1, further comprising: a second dummy power line connected to a remaining one of said power source terminals of said logic circuit; and a second control transistor connected between said second dummy power line and said second power line, said second control transistor having a threshold greater than thresholds of said field effect transistors of said logic circuit.

Claim 4

A circuit according to claim 1, further comprising a capacitor connected between said first dummy power line and said first power line providing capacitance in addition to any parasitic capacitance between the first dummy power line and the first power line.

Claim 5

A circuit according to claim 2, further comprising first and second capacitors respectively connected between said first and second dummy power lines and said first and second power lines.

Claim 6

The circuit of claim 2 further comprising a first clock signal applied to said first high threshold transistor; and a second clock signal applied to said second high threshold transistor.

Claim 7

The circuit of claim 5 wherein: said second clock signal is said first clock signal inverted.

Claim 8

A circuit comprising: a first logic circuit having a logic circuit element comprised of a plurality of field effect transistors; first and second power source lines for supplying power to said first logic circuit, with said first power line connected to a power source and with said second power line connected to a ground; a first dummy power line connected to one of a plurality of power source terminals of said logic circuit; a first control transistor connected between said first dummy power line and said first power line and having a threshold greater than thresholds at the field effect transistors of the first logic circuits; a second dummy power line connected to a remaining one of said power source terminals of said first logic circuit; a second control transistor connected between said first dummy power line and said second power line having a threshold substantially greater than thresholds of said field effect transistors of said first logic circuit; a second logic circuit, an operation of which is controlled by an output from said first logic circuit; said second logic circuit having power source terminals connected to said first and second power source lines.

Claim 9

A circuit comprising: a first logic circuit having a logic circuit element comprised of a plurality of field effect transistors; first and second power source lines for supplying power to said first logic circuit, with said first power line connected to a power source and with said second power line connected to a ground; a first dummy power line connected to one of a plurality of power source terminals of said logic circuit; a first control transistor connected between said first dummy power line and said first power line and having a threshold greater than thresholds at the field effect transistors of the first logic circuits; a second dummy power line connected to a remaining one of said power source terminals of said first logic circuit; a second control transistor connected between said first dummy power line and said second power line having a threshold substantially greater than thresholds of said field effect transistors of said first logic circuit; a second logic circuit, an operation of which is controlled by an output from said first logic circuit; said second logic circuit having power source terminals connected to said first and second power source lines.

Claim 10

A circuit according to claim 7, wherein said second logic circuit comprises: a plurality of field effect transistors with one of a plurality of power source terminals of said first logic circuit connected to said first dummy power line; and a third control transistor connected between said first dummy power line and said first power line.

Claim 11

A circuit according to claim 8, wherein a remaining one of said power source terminals of said second logic circuit is connected to said second dummy power line, and a fourth control transistor connected between said second dummy power line and said second power line and having a threshold substantially greater than thresholds of said field effect transistors of said first and second logic circuits.

Claim 12

A circuit layout comprising a plurality of logic blocks each having a control circuit block formed on an integrated circuit substrate, with each of said logic circuit blocks including a logic circuit having a logic circuit element comprised of a plurality of field effect transistors; first and second power source lines for supplying power to said low-threshold logic circuit with said first power line connected to a power source and with said second power line connected to a ground; a first dummy power line connected to one of a plurality of power source terminals of said logic circuit, and a second dummy power line connected to a remaining one of said power source terminals of said logic circuit, and with said control circuit block including a first field effect control transistor arranged between said first dummy power line and said first power line, with said first control transistor having a threshold substantially greater than thresholds of said field effect transistors of said logic circuit, and a second field effect control transistor arranged between said second dummy power line and said second power line with said first control transistor having a threshold substantially greater than thresholds of said field effect transistors of said logic circuit, with said plurality of control circuit blocks connected to said logic circuit block.

Claim 13

A circuit layout comprising a plurality of logic blocks each having a control circuit block formed on an integrated circuit substrate, with each of said logic circuit blocks including a logic circuit having a logic circuit element comprised of a plurality of field effect transistors; first and second power source lines for supplying power to said low-threshold logic circuit with said first power line connected to a power source and with said second power line connected to a ground; a first dummy power line connected to one of a plurality of power source terminals of said logic circuit, and a second dummy power line connected to a remaining one of said power source terminals of said logic circuit, and with said control circuit block including a first field effect control transistor arranged between said first dummy power line and said first power line, with said first control transistor having a threshold substantially greater than thresholds of said field effect transistors of said logic circuit, and a second field effect control transistor arranged between said second dummy power line and said second power line with said first control transistor having a threshold substantially greater than thresholds of said field effect transistors of said logic circuit, with said plurality of control circuit blocks connected to said logic circuit block.

Claim 14

A logic circuit comprising at least first and second stages, each of which comprises a low-threshold logic circuit having a plurality of logic circuit elements, each of said logic circuit elements being comprised of a plurality of field effect transistors; first and second power lines for supplying power to said low threshold logic circuit, said first power line being connected to a power source, said second power line being connected to a ground; a dummy power line being connected to one of power source terminals of said low-threshold logic circuit; and a high-threshold control transistor being connected to one of said power line, said high-threshold control transistor having a threshold substantially greater than that of said field effect transistors of said low-threshold logic circuit, said first stage comprising: a first low-threshold logic circuit having a plurality of logic circuit elements, each of said logic circuit elements being comprised of a plurality of field effect transistors, one of plural power source terminals of said first low-threshold logic circuit being connected to a first dummy power line, and the remaining one of said plural power source terminals of said first low-threshold logic circuit being connected to said second power line; a first high-threshold control transistor being connected between said first dummy power line and said first power line, said first high-threshold control transistor having a threshold substantially greater than that of said field effect transistors of said first low-threshold logic circuit; and said second stage, next to said first stage, comprising: a second low-threshold logic circuit having a plurality of logic circuit elements, each of said logic circuit elements being comprised of a plurality of field effect transistors, one of said plural power source terminals of said second low-threshold logic circuit being connected to a second dummy power line, and the remaining one of said plural power source terminals of said second low-threshold logic circuit being connected to said first power line; a second high-threshold control transistor being connected between said second dummy power line and said second power line, said second high-threshold control transistor having a threshold substantially greater than that of said field effect transistors of said second low-threshold logic circuit.

Claim 15

A logic circuit comprising at least first and second stages, each of which comprises a low-threshold logic circuit having a plurality of logic circuit elements, each of said logic circuit elements being comprised of a plurality of field effect transistors; first and second power lines for supplying power to said low threshold logic circuit, said first power line being connected to a power source, said second power line being connected to a ground; a dummy power line being connected to one of power source terminals of said low-threshold logic circuit; and a high-threshold control transistor being connected to one of said power line, said high-threshold control transistor having a threshold substantially greater than that of said field effect transistors of said low-threshold logic circuit, said first stage comprising: a first low-threshold logic circuit having a plurality of logic circuit elements, each of said logic circuit elements being comprised of a plurality of field effect transistors, one of plural power source terminals of said first low-threshold logic circuit being connected to a first dummy power line, and the remaining one of said plural power source terminals of said first low-threshold logic circuit being connected to said second power line; a first high-threshold control transistor being connected between said first dummy power line and said first power line, said first high-threshold control transistor having a threshold substantially greater than that of said field effect transistors of said first low-threshold logic circuit; and said second stage, next to said first stage, comprising: a second low-threshold logic circuit having a plurality of logic circuit elements, each of said logic circuit elements being comprised of a plurality of field effect transistors, one of said plural power source terminals of said second low-threshold logic circuit being connected to a second dummy power line, and the remaining one of said plural power source terminals of said second low-threshold logic circuit being connected to said first power line; a second high-threshold control transistor being connected between said second dummy power line and said second power line, said second high-threshold control transistor having a threshold substantially greater than that of said field effect transistors of said second low-threshold logic circuit.