US4999529A
Expired / Lapsed
US
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Programmable logic level input buffer
Assignee: Nokia Bell Labs
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Filing: 1989-06-30
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Granted: 1991-03-12
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Expires: 2009-06-30
Abstract
Abstract An integrated circuit input buffer is adapted to operate at either of two input levels, typically either TTL or CMOS logic levels. This is accommplished by switching an additional transistor (e.g. 15) into a path between the output node (e.g. 12) and a power supply voltage (e.g. V DD ), thereby changing the ratio of the pull-up to pull-down devices. The desired input level may be selected after the manufacture of the device, as by applying a voltage to a package terminal, or by programming a register during operation of the integrated circuit.
Inventors
- 👤 James V. Morgan, Jr.
- 👤 Glen E. Offord
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:09
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018585
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
163 words
An integrated circuit including at least one input buffer having an input node and an output node, with said buffer comprising: a first input transistor of a given conductivity type having a gate coupled to said input node, and being coupled to pull the output node toward a first power supply voltage; and a second transistor coupled to pull the output node toward a second power supply voltage; with the input switching level of said buffer being influenced by the ratio of the impedances of the first and second transistors, characterized in that said input buffer further comprises: a third transistor of said given conductivity type having its drain connected to the drain of said second transistor, and its gate coupled to said input node and means for providing a level select signal for switching the channel of said third transistor into a path between said output node and a power supply voltage, whereby the input switching level of said buffer is selected.
Claim 2
Dependent Claim
163 words
An integrated circuit including at least one input buffer having an input node and an output node, with said buffer comprising: a first input transistor of a given conductivity type having a gate coupled to said input node, and being coupled to pull the output node toward a first power supply voltage; and a second transistor coupled to pull the output node toward a second power supply voltage; with the input switching level of said buffer being influenced by the ratio of the impedances of the first and second transistors, characterized in that said input buffer further comprises: a third transistor of said given conductivity type having its drain connected to the drain of said second transistor, and its gate coupled to said input node and means for providing a level select signal for switching the channel of said third transistor into a path between said output node and a power supply voltage, whereby the input switching level of said buffer is selected.
Claim 3
Dependent Claim
31 words
The integrated circuit of claim 1 wherein said second transistor has the opposite conductivity type as said given type, and said second transistor has its gate coupled to said input node.
Claim 4
Dependent Claim
29 words
The integrated circuit of claim 1 wherein said second transistor has said given conductivity type, and said second transistor has its gate coupled to said second power supply voltage.
Claim 5
Dependent Claim
36 words
The integrated circuit of claim 1 wherein said means for switching comprises a fourth transistor having its source coupled to said first power supply voltage, and its drain coupled to the source of said third transistor.
Claim 6
Dependent Claim
18 words
The integrated circuit of claim 1 wherein said level select signal is generated externally to said integrated circuit.
Claim 7
Dependent Claim
17 words
The integrated circuit of claim 1 wherein said level select signal is generated on said integrated circuit.
Claim 8
Dependent Claim
21 words
The integrated circuit of claim 6 wherein said level select signal is generated by a comparator located on said integrated circuit.
Claim 9
Dependent Claim
21 words
The integrated circuit of claim 6 wherein said level select signal is generated by a register located on said integrated circuit.
Claim 10
Dependent Claim
193 words
An integrated circuit including at least one input buffer having an input node and an output node, with said buffer comprising: a first input transistor of a given conductivity type having a gate coupled to said input node, and being coupled to pull the output node toward a first power supply voltage; and a second transistor coupled to pull the output node toward a second power supply voltage; with the input switching level of said buffer being influenced by the ratio of the impedances of the first and second transistors, characterized in that said input buffer further comprises: a third transistor of said given conductivity type having its gate coupled to said input node, and its source coupled to said first power supply voltage; and a fourth transistor having its source coupled to the drain of said third transistor, and its drain connected to said output node; and means for providing a level select signal to the gate of said fourth transistor, for switching the channel of said third transistor into a path between said output node and said first power supply voltage, whereby the input switching level of said buffer is selected.
Claim 11
Dependent Claim
193 words
An integrated circuit including at least one input buffer having an input node and an output node, with said buffer comprising: a first input transistor of a given conductivity type having a gate coupled to said input node, and being coupled to pull the output node toward a first power supply voltage; and a second transistor coupled to pull the output node toward a second power supply voltage; with the input switching level of said buffer being influenced by the ratio of the impedances of the first and second transistors, characterized in that said input buffer further comprises: a third transistor of said given conductivity type having its gate coupled to said input node, and its source coupled to said first power supply voltage; and a fourth transistor having its source coupled to the drain of said third transistor, and its drain connected to said output node; and means for providing a level select signal to the gate of said fourth transistor, for switching the channel of said third transistor into a path between said output node and said first power supply voltage, whereby the input switching level of said buffer is selected.
Claim 12
Dependent Claim
31 words
The integrated circuit of claim 9 wherein said second transistor has the opposite conductivity type as said given type, and said second transistor has its gate coupled to said input node.
Claim 13
Dependent Claim
29 words
The integrated circuit of claim 9 wherein said second transistor has said given conductivity type, and said second transistor has its gate coupled to said second power supply voltage.
Claim 14
Dependent Claim
18 words
The integrated circuit of claim 9 wherein said level select signal is generated externally to said integrated circuit.
Claim 15
Dependent Claim
17 words
The integrated circuit of claim 9 wherein said level select signal is generated on said integrated circuit.
Claim 16
Dependent Claim
21 words
The integrated circuit of claim 13, wherein said level select signal is generated by a comparator located on said integrated circuit.
Claim 17
Dependent Claim
21 words
The integrated circuit of claim 13 wherein said level select signal is generated by a register located on said integrated circuit.
Claim 18
Dependent Claim
146 words
An integrated circuit including at least one input buffer having an input node and an output node, with said buffer comprising: a first input transistor of a given conductivity type having a gate coupled to said input node, and being coupled to pull the output node toward a first power supply voltage; and a second transistor coupled to pull the output node toward a second power supply voltage; with the input switching level of said buffer being influenced by the ratio of the impedances of the first and second transistors, characterized in that said input buffer further comprises: a third transistor of said given conductivity type having its source coupled to a given power supply voltage, its drain connected to said common output node; and its gate coupled to means for providing a level select signal, whereby the input switching level of said buffer is selected.
Claim 19
Dependent Claim
146 words
An integrated circuit including at least one input buffer having an input node and an output node, with said buffer comprising: a first input transistor of a given conductivity type having a gate coupled to said input node, and being coupled to pull the output node toward a first power supply voltage; and a second transistor coupled to pull the output node toward a second power supply voltage; with the input switching level of said buffer being influenced by the ratio of the impedances of the first and second transistors, characterized in that said input buffer further comprises: a third transistor of said given conductivity type having its source coupled to a given power supply voltage, its drain connected to said common output node; and its gate coupled to means for providing a level select signal, whereby the input switching level of said buffer is selected.
Claim 20
Dependent Claim
31 words
The integrated circuit of claim 16 wherein said second transistor has the opposite conductivity type as said given type, and said second transistor has its gate coupled to said input node.
Claim 21
Dependent Claim
29 words
The integrated circuit of claim 16 wherein said second transistor has said given conductivity type, and said second transistor has its gate coupled to said second power supply voltage.
Claim 22
Dependent Claim
18 words
The integrated circuit of claim 16 wherein said level select signal is generated externally to said integrated circuit.
Claim 23
Dependent Claim
17 words
The integrated circuit of claim 16 wherein said level select signal is generated on said integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-03-11 | 1994-09-10 | 1995-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-03-11 | 1998-09-10 | 1999-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-03-11 | 2002-09-10 | 2003-03-12 | $7700.00 | Window Closed / Lapsed |