Data latch circuit

Abstract

Abstract PURPOSE:To attain low power consumption without giving limit conditions to the level of input data by allowing an input buffer circuit to be in operating state only when the input data is fed to a latch circuit, that is, to be in the normal operation while being connected to a power supply. CONSTITUTION:Either a P-channel MOSFET31 or an N-channel MOSFET32 constituting a CMOS inverter 33 is turned on by an output of a clocked CMOS inverter 38 in the data holding operation by a latch circuit 12. When a current path is produced between an output terminal 26 and a VDD supply terminal or a ground potential supply terminal in a series circuit 213 of the final stage of an input buffer circuit 11 in this case, a through-current flows between the VDD and ground in a circuit combining the input buffer circuit 11 and the latch circuit 12, but no current path is produced both for the P-channel and the N-channel side of each series circuit 21 in this period, and each output terminal 26 is brought into a high impedance state and no through-current is produced.

Inventors

• 👤 Kenji Takaguchi
• 👤 高口　憲二
• 👤 Koji Saito
• 👤 斉藤　幸治

Bibliographic Details