US6433584B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit
Assignee: Renesas Electronics Corp
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Filing: 1998-06-18
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Granted: 2002-08-13
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Expires: 2018-06-18
Abstract
Abstract The present invention includes a logic circuit block operated in synchronism with a clock signal, power supply switches which supply power to the logic circuit block, and a switch control circuit which controls the power supply switches. The switch control circuit switch-controls the power supply switches so as to bring a period shorter than the cycle of the clock signal to an on operation period in synchronism with a clock signal. When the logic circuit block is supposed to be activated in synchronism with a clock signal having a frequency lower than a clock signal frequency for defining the maximum operation speed of the logic circuit block, the logic circuit block does not develop a malfunction theoretically if capable of operation for each cycle of the clock signal at least only for a time interval defined by the clock signal frequency of the maximum operation speed. Since the supplying of operating power to the logic circuit block is cut off according to the clock signal frequency except for a period necessary for a circuit operation, leak current that will flow through each turned-off transistor in the meantime, can be significantly reduced.
Inventors
- 👤 Hiroshi Hatae
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:51
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0016
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
134 words
A semiconductor integrated circuit, comprising: a logic circuit block operatively connected to a clock signal source; at least one power supply switch operatively connected to supply power to said logic circuit block; and a switch control circuit for controlling said power supply switch, wherein said clock signal source supplies a first clock signal and a second clock signal, said second clock signal having a cycle time that is longer than said first clock signal, and said switch control circuit switch-controls said power supply switch so as to selectively engage said logic circuit block with one of said first and second clock signals so as to operate said logic circuit block in synchronism with-the first clock signal in a first operating mode and in synchronism with the second clock signal in a second operating mode.
Claim 2
Dependent Claim
134 words
A semiconductor integrated circuit, comprising: a logic circuit block operatively connected to a clock signal source; at least one power supply switch operatively connected to supply power to said logic circuit block; and a switch control circuit for controlling said power supply switch, wherein said clock signal source supplies a first clock signal and a second clock signal, said second clock signal having a cycle time that is longer than said first clock signal, and said switch control circuit switch-controls said power supply switch so as to selectively engage said logic circuit block with one of said first and second clock signals so as to operate said logic circuit block in synchronism with-the first clock signal in a first operating mode and in synchronism with the second clock signal in a second operating mode.
Claim 3
Dependent Claim
35 words
The semiconductor integrated circuit as claimed in claim 1 , wherein a threshold voltage of said power supply switch is greater than a threshold voltage of each of transistors which constitute said logic circuit block.
Claim 4
Dependent Claim
19 words
The semiconductor integrated circuit as claimed in claim 2 , wherein said logic circuit block is a CMOS circuit.
Claim 5
Dependent Claim
44 words
The semiconductor integrated circuit as claimed in claim 2 , wherein the threshold voltage of said power supply switch is set greater than the threshold voltage of each of the transistors which constitute said logic circuit block, by changing a substrate or well potential.
Claim 6
Dependent Claim
47 words
The semiconductor integrated circuit as claimed in claim 2 , further including setting means for programnmably setting an on operation period of said power supply switch, and wherein said switch control circuit determines the on operation period, based on a set value supplied from said setting means.
Claim 7
Dependent Claim
49 words
The semiconductor integrated circuit as claimed in claim 2 , wherein said switch control circuit effects the switch control on said power switch when a first operation mode is specified, and brings said power supply switch to an on state at all times when a second operation is specified.
Claim 8
Dependent Claim
162 words
The semiconductor integrated circuit as claimed in claim 2 , further including a clock control circuit which is supplied with a first clock signal and a second clock signal higher than the first clock signal in frequency and which supplies the first clock signal to said logic circuit block when a first operation mode is specified, supplies the second clock signal to said logic circuit block when a second operation mode is specified, and stops the supply of the clock signals to said logic circuit block when a third operation mode is specified, and wherein said switch control circuit effects the switch control on said power supply switch when the first operation mode is specified, brings said power supply switch to an on state at all times when the second operation mode is specified, and turns on said power supply switch for each predetermined period when the third operation mode is specified, thereby refreshing an internal node in said logic circuit block.
Claim 9
Dependent Claim
49 words
The semiconductor integrated circuit as claimed in claim 2 , wherein said power supply switch is one switch selected from a first switch connected to a power-supply terminal on the high-potential side and a second switch connected to a power-supply terminal on the low-potential side, or both switches thereof.
Claim 10
Dependent Claim
47 words
The semiconductor integrated circuit as claimed in claim 1 , further including setting means for programmably setting an on operation period of said power supply switch, and wherein said switch control circuit determines the on operation period, based on a set value supplied from said setting means.
Claim 11
Dependent Claim
49 words
The semiconductor integrated circuit as claimed in claim 1 , wherein said switch control circuit effects the switch control on said power switch when a first operation mode is specified, and brings said power supply switch to an on state at all times when a second operation is specified.
Claim 12
Dependent Claim
62 words
The semiconductor integrated circuit as claimed in claim 10 , further including setting means for programmably setting an on operation period of said power supply switch subjected to the switch control, and wherein said switch control circuit determines the on operation period of said power supply switch in the first operation mode, based on a set value supplied from said setting means.
Claim 13
Dependent Claim
74 words
The semiconductor integrated circuit as claimed in claim 11 , further including a clock control circuit which is supplied with a first clock signal and a second clock signal higher than the first clock signal in frequency and which supplies the first clock signal to said logic circuit block when the first operation mode is specified and supplies the second clock signal to said logic circuit block when the second operation mode is specified.
Claim 14
Dependent Claim
26 words
The semiconductor integrated circuit as claimed in claim 12 , wherein said sequence circuit is operated in synchronism with a first edge of the clock signal.
Claim 15
Dependent Claim
62 words
The data processing system as claimed in claim 12 , wherein said plurality of logic circuit blocks respectively constitute processors and said each processor includes a CPU subjected to clock control and power-supply control responsive to the high-speed, low-speed and standby modes, and an interrupt control circuit subjected to the clock control and power-supply control responsive to the highspeed and low-speed modes.
Claim 16
Dependent Claim
162 words
The semiconductor integrated circuit as claimed in claim 1 , further including a clock control circuit which is supplied with a first clock signal and a second clock signal higher than the first clock signal in frequency and which supplies the first clock signal to said logic circuit block when a first operation mode is specified, supplies the second clock signal to said logic circuit block when a second operation mode is specified, and stops the supply of the clock signals to said logic circuit block when a third operation mode is specified, and wherein said switch control circuit effects the switch control on said power supply switch when the first operation mode is specified, brings said power supply switch to an on state at all times when the second operation mode is specified, and turns on said power supply switch for each predetermined period when the third operation mode is specified, thereby refreshing an internal node in said logic circuit block.
Claim 17
Dependent Claim
49 words
The semiconductor integrated circuit as claimed in claim 1 , wherein said power supply switch is one switch selected from a first switch connected to a power-supply terminal on the high-potential side and a second switch connected to a power-supply terminal on the low-potential side, or both switches thereof.
Claim 18
Dependent Claim
61 words
A semiconductor integrated circuit as claimed in claim 1 , wherein said switch control circuit further controls said power supply switch so as to clear said logic circuit block in said first operating mode, and to supply power to said logic circuit block for a period shorter than the cycle time of the second clock signal during the second operating mode.
Claim 19
Dependent Claim
156 words
A semiconductor integrated circuit, comprising: a logic circuit block including a combinational circuit and a sequence circuit operatively connected to a clock signal source; at least one transistor operatively connected to control the supplying of power from a power supply to the combinational circuit and the sequence circuit of said logic circuit block; and a switch control circuit which controls said transistor, wherein said clock signal source includes a first clock signal and a second clock signal, said second clock signal having a cycle time that is longer than said first clock signal, and said switch control circuit switch-controls said transistor so as to selectively engage the combinational circuit and sequence circuit with one of said first and second clock signals so as to operate the combinational circuit and sequence circuit in synchronism with the first clock signal in a first operating mode and in synchronism with the second clock signal in a second operating mode.
Claim 20
Dependent Claim
156 words
A semiconductor integrated circuit, comprising: a logic circuit block including a combinational circuit and a sequence circuit operatively connected to a clock signal source; at least one transistor operatively connected to control the supplying of power from a power supply to the combinational circuit and the sequence circuit of said logic circuit block; and a switch control circuit which controls said transistor, wherein said clock signal source includes a first clock signal and a second clock signal, said second clock signal having a cycle time that is longer than said first clock signal, and said switch control circuit switch-controls said transistor so as to selectively engage the combinational circuit and sequence circuit with one of said first and second clock signals so as to operate the combinational circuit and sequence circuit in synchronism with the first clock signal in a first operating mode and in synchronism with the second clock signal in a second operating mode.
Claim 21
Dependent Claim
31 words
The semiconductor integrated circuit as claimed in claim 18 , wherein a threshold voltage of said transistor is greater than that of each of transistors which constitute said logic circuit block.
Claim 22
Dependent Claim
37 words
The semiconductor integrated circuit as claimed in claim 19 , wherein the threshold voltage of said transistor is set greater than that of each transistor constituting said logic circuit block by changing a substrate or well potential.
Claim 23
Dependent Claim
17 words
The semiconductor integrated circuit as claimed in claim 20 , wherein said transistor is a MOS transistor.
Claim 24
Dependent Claim
59 words
A semiconductor integrated circuit as claimed in claim 18 , wherein said switch control circuit further controls said transistor so as to clear said logic circuit block in said first operating mode, and to supply power to said logic circuit block for a period shorter than the cycle time of the second clock signal during the second operating mode.
Claim 25
Dependent Claim
173 words
A semiconductor integrated circuit, comprising: a logic circuit block including a combination circuit and a sequence circuit operatively connected to a clock signal source; at least one MOS transistor operatively connected to control the supplying of power from a power supply to the combinational circuit and the sequence circuit of said logic circuit block; a switch control circuit which controls said MOS transistor; and a control signal, wherein said clock signal source includes a first clock signal and a second clock signal, said second clock signal having a cycle time that is longer than said first clock signal, and said switch control circuit is operatively connected to receive the control signal and in response thereto switch-control said MOS transistor so as to selectively engage the combinational circuit and sequence circuit with one of said first and second clock signals and thereby operate the combinational circuit and sequence circuit in synchronism with the first clock signal in a first operating mode and in synchronism with the second clock signal in a second operating mode.
Claim 26
Dependent Claim
173 words
A semiconductor integrated circuit, comprising: a logic circuit block including a combination circuit and a sequence circuit operatively connected to a clock signal source; at least one MOS transistor operatively connected to control the supplying of power from a power supply to the combinational circuit and the sequence circuit of said logic circuit block; a switch control circuit which controls said MOS transistor; and a control signal, wherein said clock signal source includes a first clock signal and a second clock signal, said second clock signal having a cycle time that is longer than said first clock signal, and said switch control circuit is operatively connected to receive the control signal and in response thereto switch-control said MOS transistor so as to selectively engage the combinational circuit and sequence circuit with one of said first and second clock signals and thereby operate the combinational circuit and sequence circuit in synchronism with the first clock signal in a first operating mode and in synchronism with the second clock signal in a second operating mode.
Claim 27
Dependent Claim
60 words
A semiconductor integrated circuit as claimed in claim 23 , wherein said switch control circuit further controls said MOS transistor so as to clear said logic circuit block in said first operating mode, and to supply power to said logic circuit block for a period shorter than the cycle time of the second clock signal during the second operating mode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-08-12 | 2006-02-11 | 2006-08-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-08-12 | 2010-02-11 | 2010-08-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-08-12 | 2014-02-11 | 2014-08-13 | $7700.00 | Window Closed / Lapsed |