US6472278B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for creating a voltage threshold in a FET
Assignee: NXP USA Inc
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Filing: 2000-10-04
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Granted: 2002-10-29
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Expires: 2020-10-04
Abstract
Abstract A method of fabricating a field effect transistor including doping a continuous blanket layer in a semiconductor substrate structure adjacent the surface to include a source area and a drain area spaced from the source area. A high dielectric constant insulator layer is positioned on the surface of the semiconductor substrate structure overlying the continuous blanket layer to define a gate area between the source and drain areas. A gate contact on the insulator layer is selected to provide a work function difference that depletes the doped layer beneath the insulator layer. Further, the doped layer depth and dosage are designed such that the doped layer is depleted beneath the insulator layer by the selected work function difference of the gate contact and the semiconductor substrate.
Inventors
- 👤 Daniel S. Marshall
- 👤 William J. Ooms
- 👤 Jerald A. Hallmark
- 👤 Yang Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:15
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/60; H10D30/637; H10D64/00; H10D64/60; H10D64/66; H10D64/667; H10D64/668; H10D64/68; H10D64/691
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
106 words
A method of fabricating a field effect transistor comprising the steps of: providing a semiconductor substrate with a surface; providing a doped region in the semiconductor substrate structure adjacent the surface including a source area and a drain area spaced from the source area; positioning a high dielectric constant insulator layer on the surface of the semiconductor substrate structure overlying the doped region and defining a gate area between the source and drain areas; and positioning a gate contact on the insulator layer, said gate contact having a work function wherein said work function is chosen to set the threshold voltage of said field effect transistor.
Claim 2
Independent Claim
106 words
A method of fabricating a field effect transistor comprising the steps of: providing a semiconductor substrate with a surface; providing a doped region in the semiconductor substrate structure adjacent the surface including a source area and a drain area spaced from the source area; positioning a high dielectric constant insulator layer on the surface of the semiconductor substrate structure overlying the doped region and defining a gate area between the source and drain areas; and positioning a gate contact on the insulator layer, said gate contact having a work function wherein said work function is chosen to set the threshold voltage of said field effect transistor.
Claim 3
Dependent Claim
58 words
A method of fabricating a field effect transistor as claimed in claim 1 wherein the step of positioning the high dielectric constant insulator layer on the surface of the semiconductor substrate structure includes forming an insulator layer with a dielectric constant of at least 25 and positioning the insulator layer on the surface of the semiconductor substrate structure.
Claim 4
Dependent Claim
60 words
A method of fabricating a field effect transistor as claimed in claim 1 wherein the step of providing a doped region in tho semiconductor substrate structure includes providing doping with a depth and dosage such that the doped region is substantially depleted beneath the insulator layer by a work function difference of the gate contact and the semiconductor substrate structure.
Claim 5
Dependent Claim
30 words
A method of fabricating a field effect transistor as claimed in claim 1 wherein the step of providing the semiconductor substrate structure includes providing a supporting substrate formed of silicon.
Claim 6
Dependent Claim
35 words
A method of fabricating a field effect transistor as-claimed in claim 4 wherein the step of positioning the high dielectric constant insulator layer includes forming a high dielectric constant insulator layer of (CaSr)TiO 3 .
Claim 7
Dependent Claim
35 words
A method of fabricating a field effect transistor as claimed in claim 4 wherein the step of positioning the gate contact includes positioning a layer of molybdenum silicide on the high dielectric constant insulator layer.
Claim 8
Dependent Claim
35 words
A method of fabricating a field effect transistor as claimed in claim 1 wherein the step of positioning the gate contact includes positioning a layer of conductive oxide on the high dielectric constant insulator layer.
Claim 9
Dependent Claim
35 words
A method of fabricating a field effect transistor as claimed in claim 1 wherein the step of positioning the gate contact includes positioning a layer of conductive perovskite on the high dielectric constant insulator layer.
Claim 10
Dependent Claim
39 words
A method of fabricating a field effect transistor as claimed in claim 1 wherein the step of providing a doped region in the semiconductor substrate structure includes one of implanting and diffusing a dopant in the semiconductor substrate structure.
Claim 11
Independent Claim
131 words
A method of fabricating a low overlap capacitance field effect transistor comprising the steps of: providing a semiconductor substrate structure with a surface; doping a source area and a drain area spaced from the source area in the semiconductor substrate structure adjacent the surface, and defining a non-doped area therebetween; positioning a high dielectric constant insulator layer on the surface of the semiconductor substrate structure generally overlying the non-doped area and defining a gate area including the non-doped area and portions of the source and drain areas; positioning a gate contact on the insulator layer; and selecting materials for the semiconductor substrate structure and the gate contact to provide a work function difference therebetween that depletes the portions of the source and drain areas beneath the high dielectric constant insulator layer.
Claim 12
Independent Claim
131 words
A method of fabricating a low overlap capacitance field effect transistor comprising the steps of: providing a semiconductor substrate structure with a surface; doping a source area and a drain area spaced from the source area in the semiconductor substrate structure adjacent the surface, and defining a non-doped area therebetween; positioning a high dielectric constant insulator layer on the surface of the semiconductor substrate structure generally overlying the non-doped area and defining a gate area including the non-doped area and portions of the source and drain areas; positioning a gate contact on the insulator layer; and selecting materials for the semiconductor substrate structure and the gate contact to provide a work function difference therebetween that depletes the portions of the source and drain areas beneath the high dielectric constant insulator layer.
Claim 13
Dependent Claim
87 words
A method of fabricating a low overlap capacitance field effect transistor as claimed in claim 11 wherein the step of doping the source area and the drain area spaced from the source area in the semiconductor substrate structure includes doping a source area and a spaced apart drain area with a depth and dosage such that the portions of the source and drain areas beneath the high dielectric constant insulator layer are depleted by a work function difference of the gate contact and the semiconductor substrate structure.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-10-28 | 2006-04-29 | 2006-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-10-28 | 2010-04-29 | 2010-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-10-28 | 2014-04-29 | 2014-10-29 | $7700.00 | Window Closed / Lapsed |