Patent US6445205B1 successfully refreshed from Google Patents.
US6445205B1
Expired / Lapsed
US
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Method of testing integrated circuits
Assignee: Unwired Planet LLC
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Filing: 1999-11-22
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Granted: 2002-09-03
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Expires: 2019-11-22
Abstract
Abstract An integrated circuit which allows for ease of testing thereof, and a method of such testing. The integrated circuit includes a linear shift register without feedback, which converts signals on a bus into a serial bitstream. The integrated circuit has an output pin connected to the linear shift register to receive the serial bitstream thereon. The method of testing the chip includes supplying test inputs to the chip, reading the serial bitstream data during the test from an output pin of the integrated circuit, and comparing the output data in a test device with an expected bitstream. The signals on the bus under investigation can be monitored continually throughout the test. In the event that a fault is discovered, the test can be terminated much more quickly than when using a device which requires the test to be completed before any data can be read out.
Inventors
- 👤 Per Fremrot
- 👤 Mats Frännhagen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:04
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/221; G06F11/2236
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
114 words
A method of testing an integrated circuit comprising: an internal bus, having a plurality of lines; a linear shift register, having its inputs connected to respective lines of the bus, and adapted to convert signals on the lines of the bus into a serial bitstream; and an output pin, connected to the linear shift register and adapted to receive the serial bitstream thereon, and the method comprising: supplying test inputs to the integrated circuit; on the integrated circuit, converting signals on the internal bus thereof into the serial bitstream; reading the serial bitstream from the output pin of the integrated circuit; and in a test device, comparing the read bitstream with a known bitstream.
Claim 2
Independent Claim
114 words
A method of testing an integrated circuit comprising: an internal bus, having a plurality of lines; a linear shift register, having its inputs connected to respective lines of the bus, and adapted to convert signals on the lines of the bus into a serial bitstream; and an output pin, connected to the linear shift register and adapted to receive the serial bitstream thereon, and the method comprising: supplying test inputs to the integrated circuit; on the integrated circuit, converting signals on the internal bus thereof into the serial bitstream; reading the serial bitstream from the output pin of the integrated circuit; and in a test device, comparing the read bitstream with a known bitstream.
Claim 3
Dependent Claim
41 words
A method as claimed in claim 1 , wherein the integrated circuit has a Harvard architecture, having a processor and having a program bus and a data bus connected to the processor, and wherein the internal bus is said data bus.
Claim 4
Dependent Claim
32 words
A method as claimed in claim 1 , wherein the integrated circuit has a von Neumann architecture, having at least one internal bus which is not observable on pins of the circuit.
Claim 5
Dependent Claim
50 words
A method as claimed in claim 1 , wherein the linear shift register comprises a plurality of registers, each register receiving an input from a respective adder, and each adder being connected to a respective line of the bus, the registers being clocked at the data rate of the bus.
Claim 6
Dependent Claim
29 words
A method as claimed in claim 4 , wherein data are added to the shift register only when each register also receives an enable signal at an input thereof.
Claim 7
Dependent Claim
33 words
A method as claimed in claim 4 , wherein data are added to the shift register through logic gates, only when each logic gate also receives an enable signal at an input thereof.
Claim 8
Independent Claim
70 words
A method of testing an integrated circuit, the method comprising the steps of: supplying test inputs to the integrated circuit; converting, via a linear shift register on the integrated circuit, signals on an internal bus of the integrated circuit into a serial bitstream; reading the serial bitstream from a single output pin of the integrated circuit; and in a test device, comparing the read serial bitstream to a known bitstream.
Claim 9
Independent Claim
70 words
A method of testing an integrated circuit, the method comprising the steps of: supplying test inputs to the integrated circuit; converting, via a linear shift register on the integrated circuit, signals on an internal bus of the integrated circuit into a serial bitstream; reading the serial bitstream from a single output pin of the integrated circuit; and in a test device, comparing the read serial bitstream to a known bitstream.
Claim 10
Dependent Claim
40 words
A method as claimed in claim 7 , further comprising a processor, and a program bus and a data bus connected to the processor, and wherein the internal bus is the data bus and the circuit employs a Harvard architecture.
Claim 11
Dependent Claim
33 words
A method as claimed in claim 7 , wherein the integrated circuit implements a von Neumann architecture and has at least one internal bus that is not observable on pins of the circuit.
Claim 12
Dependent Claim
50 words
A method as claimed in claim 7 , wherein the linear shift register comprises a plurality of registers, each register receiving an input from a respective adder, and each adder being connected to a respective line of the bus, the registers being clocked at the data rate of the bus.
Claim 13
Dependent Claim
28 words
A method as claimed in claim 10 , wherein data are added to the shift register only when each register receives an enable signal at an input thereof.
Claim 14
Dependent Claim
32 words
A method as claimed in claim 10 , wherein data are added to the shift register, through logic gates, only when each logic gate receives an enable signal at an input thereof.
Claim 15
Dependent Claim
111 words
A integrated circuit comprising: an internal bus having a plurality of lines; a linear shift register having inputs connected to respective lines of the bus and being adapted to convert signals on the lines of the bus into a serial bitstream; and an output pin connected to the linear shift register, the output pin being adapted to receive the serial bitstream thereon, wherein test inputs are applied to the integrated circuit, signals on the internal bus of the integrated circuit are converted into a serial bitstream, the serial bitstream is read from the output pin, and the read serial bitstream is used to determine if the integrated circuit is functioning correctly.
Claim 16
Dependent Claim
111 words
A integrated circuit comprising: an internal bus having a plurality of lines; a linear shift register having inputs connected to respective lines of the bus and being adapted to convert signals on the lines of the bus into a serial bitstream; and an output pin connected to the linear shift register, the output pin being adapted to receive the serial bitstream thereon, wherein test inputs are applied to the integrated circuit, signals on the internal bus of the integrated circuit are converted into a serial bitstream, the serial bitstream is read from the output pin, and the read serial bitstream is used to determine if the integrated circuit is functioning correctly.
Claim 17
Dependent Claim
38 words
A circuit as claimed in claim 13 , further comprising a processor, a program bus and a data bus connected to the processor, wherein the internal bus is the data bus and the circuit employs a Harvard architecture.
Claim 18
Dependent Claim
29 words
A circuit as claimed in claim 13 , further comprising a von Neumann architecture and at least one internal bus that is not observable on pins of the circuit.
Claim 19
Dependent Claim
52 words
A circuit as claimed in claim 13 , wherein the linear shift register comprises a plurality of register, each register is adapted to receive an input from a respective adder and is clocked at a data rate of the bus, and each adder is connected to a respective line of the bus.
Claim 20
Dependent Claim
29 words
A circuit as claimed in claim 16 , wherein data are added to the linear shift register only when each register receives an enable signal at an input thereof.
Claim 21
Dependent Claim
33 words
A circuit as claimed in claim 16 , wherein data are added to the linear shift register, through logic gates, only when each logic gate receives an enable signal at an input thereof.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-02 | 2006-03-04 | 2006-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-02 | 2010-03-04 | 2010-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-02 | 2014-03-04 | 2014-09-03 | $7700.00 | Window Closed / Lapsed |