Patent US6437404B1 successfully refreshed from Google Patents.
US6437404B1
Expired / Lapsed
US
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Semiconductor-on-insulator transistor with recessed source and drain
Assignee: GlobalFoundries Inc
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Filing: 2000-08-10
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Granted: 2002-08-20
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Expires: 2020-08-10
Abstract
Abstract A fully-depleted semiconductor-on-insulator (SOI) transistor device has an SOI substrate with a buried insulator layer having a nonuniform depth relative to a top surface of the substrate, the buried insulator layer having a shallow portion closer to the top surface than deep portions of the layer. A gate is formed on a thin semiconductor layer between the top surface and the shallow portion of the insulator layer. Source and drain regions are formed on either side of the gate, the source and drain regions each being atop one of the deep portions of the buried insulator layer. The source and drain regions thereby have a greater thickness than the thin semiconductor layer. Thick silicide regions formed in the source and drain regions have low parasitic resistance. A method of making the transistor device includes forming a dummy gate structure on an SOI substrate, and using the dummy gate structure to control the depth of an implantation to form the nonuniform depth buried insulator layer.
Inventors
- 👤 Qi Xiang
- 👤 Wei Long
- 👤 Ming-Ren Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:07
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/208; H10P30/209; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/674; H10D30/6757; H10D30/6758; H10D64/00; H10D64/01; H10D64/015; H10D64/017; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01316
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
136 words
A semiconductor-on-insulator transistor device comprising: a silicon-on-insulator substrate having a top surface, the substrate including a buried insulator layer and a semiconductor layer, the buried insulator layer having a shallow portion and deep portions, wherein the shallow portion is closer to the top surface than the deep portions, and the semiconductor layer being atop the shallow portion; a gate atop the semiconductor layer; and silicide regions between the top surface and at least part of respective of the deep portions; wherein the semiconductor layer includes a source and a drain which are operatively coupled to the gate; wherein the silicide regions include a source silicide region operatively coupled to the source, and a drain silicide region operatively coupled to the drain; and wherein the silicide regions are at least partially in contact with the deep portions.
Claim 2
Dependent Claim
136 words
A semiconductor-on-insulator transistor device comprising: a silicon-on-insulator substrate having a top surface, the substrate including a buried insulator layer and a semiconductor layer, the buried insulator layer having a shallow portion and deep portions, wherein the shallow portion is closer to the top surface than the deep portions, and the semiconductor layer being atop the shallow portion; a gate atop the semiconductor layer; and silicide regions between the top surface and at least part of respective of the deep portions; wherein the semiconductor layer includes a source and a drain which are operatively coupled to the gate; wherein the silicide regions include a source silicide region operatively coupled to the source, and a drain silicide region operatively coupled to the drain; and wherein the silicide regions are at least partially in contact with the deep portions.
Claim 3
Dependent Claim
137 words
A semiconductor-on-insulator transistor device comprising: a silicon-on-insulator substrate having a top surface, the substrate including a buried insulator layer and a semiconductor layer, the buried insulator layer having a shallow portion and deep portions, wherein the shallow portion is closer to the top surface than the deep portions, and the semiconductor layer being atop the shallow portion; a gate atop the semiconductor layer; and silicide regions between the top surface and at least part of respective of the deep portions; wherein the semiconductor layer includes a source and a drain which are operatively coupled to the gate; wherein the silicide regions include a source silicide region operatively coupled to the source, and a drain silicide region operatively coupled to the drain; and wherein the source and drain silicide regions are at least partially atop the shallow portion.
Claim 4
Dependent Claim
137 words
A semiconductor-on-insulator transistor device comprising: a silicon-on-insulator substrate having a top surface, the substrate including a buried insulator layer and a semiconductor layer, the buried insulator layer having a shallow portion and deep portions, wherein the shallow portion is closer to the top surface than the deep portions, and the semiconductor layer being atop the shallow portion; a gate atop the semiconductor layer; and silicide regions between the top surface and at least part of respective of the deep portions; wherein the semiconductor layer includes a source and a drain which are operatively coupled to the gate; wherein the silicide regions include a source silicide region operatively coupled to the source, and a drain silicide region operatively coupled to the drain; and wherein the source and drain silicide regions are at least partially atop the shallow portion.
Claim 5
Dependent Claim
29 words
The transistor device of claim 2 , further comprising a buried semiconductor region at least partially between one of the silicide regions and a corresponding of the deep portions.
Claim 6
Dependent Claim
21 words
The transistor device of claim 2 , wherein the silicide regions each have a maximum thickness of at least 200 Angstroms.
Claim 7
Dependent Claim
20 words
The transistor device of claim 2 , wherein the semiconductor layer has a thickness of between 500 and 5000 Angstroms.
Claim 8
Dependent Claim
24 words
The transistor device of claim 2 , wherein the semiconductor layer has a thickness less than about ⅓ of a length of the gate.
Claim 9
Dependent Claim
15 words
The transistor device of claim 2 , wherein the gate includes a metal gate electrode.
Claim 10
Dependent Claim
17 words
The transistor device of claim 2 , wherein the semiconductor layer includes a fully depleted channel region.
Claim 11
Dependent Claim
16 words
The transistor device of claim 2 , wherein the shallow portion is wider than the gate.
Claim 12
Dependent Claim
17 words
The transistor device of claim 2 , wherein the buried insulator layer is a buried oxide layer.
Claim 13
Dependent Claim
26 words
The transistor device of claim 10 , wherein the semiconductor layer is a silicon layer and the buried oxide layer is a buried silicon oxide layer.
Claim 14
Dependent Claim
16 words
The transistor device of claim 10 , wherein the buried insulator layer is a continuous layer.
Claim 15
Dependent Claim
23 words
The transistor device of claim 10 , wherein the buried insulator layer includes transition portions between the shallow portion and the deep portions.
Claim 16
Dependent Claim
16 words
The transistor device of claim 13 , wherein the transition portions each have a curved shape.
Claim 17
Dependent Claim
23 words
The transistor device of claim 13 , wherein the source and drain silicide portions are in contact with respective of the transition portions.
Claim 18
Dependent Claim
16 words
The transistor device of claim 2 , wherein the buried insulator layer has substantially uniform thickness.
Claim 19
Dependent Claim
27 words
The transistor device of claim 2 , wherein the shallow portion is substantially parallel to the top surface, the semiconductor layer thereby having a substantially uniform thickness.
Claim 20
Dependent Claim
26 words
The transistor device of claim 2 , wherein the source and drain silicide portions are in contact with the shallow portion of the buried insulator layer.
Claim 21
Dependent Claim
38 words
The transistor device of claim 2 , wherein the source and the drain include respective source and drain extensions, and wherein the source and drain extensions are in contact with the shallow portion of the buried insulator layer.
Claim 22
Dependent Claim
157 words
A semiconductor-on-insulator transistor device comprising: a silicon-on-insulator substrate having a top surface, the substrate including a buried insulator layer and a semiconductor layer, the buried insulator layer having a shallow portion and deep portions, wherein the shallow portion is closer to the top surface than the deep portions, and the semiconductor layer being atop the shallow portion; a gate atop the semiconductor layer; and a source silicide region operatively coupled to the source, and a drain silicide region operatively coupled to the drain; wherein the semiconductor layer includes a source and a drain which are operatively coupled to the gate; wherein the source and the drain include respective source and drain extensions, and wherein the source and drain extensions are in contact with the shallow portion of the buried insulator layer; wherein the suicide regions are atop the shallow portion of the buried insulator layer; and wherein the suicide regions are in contact with the shallow portion.
Claim 23
Dependent Claim
157 words
A semiconductor-on-insulator transistor device comprising: a silicon-on-insulator substrate having a top surface, the substrate including a buried insulator layer and a semiconductor layer, the buried insulator layer having a shallow portion and deep portions, wherein the shallow portion is closer to the top surface than the deep portions, and the semiconductor layer being atop the shallow portion; a gate atop the semiconductor layer; and a source silicide region operatively coupled to the source, and a drain silicide region operatively coupled to the drain; wherein the semiconductor layer includes a source and a drain which are operatively coupled to the gate; wherein the source and the drain include respective source and drain extensions, and wherein the source and drain extensions are in contact with the shallow portion of the buried insulator layer; wherein the suicide regions are atop the shallow portion of the buried insulator layer; and wherein the suicide regions are in contact with the shallow portion.
Claim 24
Dependent Claim
23 words
The transistor device of claim 20 , wherein the buried insulator layer includes transition portions between the shallow portion and the deep portions.
Claim 25
Dependent Claim
18 words
The transistor device of claim 21 , wherein the silicide regions are atop respective of the transition portions.
Claim 26
Dependent Claim
17 words
The transistor device of claim 20 , wherein the semiconductor layer includes a fully depleted channel layer.
Claim 27
Dependent Claim
186 words
A semiconductor-on-insulator transistor device comprising: a silicon-on-insulator substrate having a top surface, the substrate including a buried insulator layer and a semiconductor layer, the buried insulator layer having a shallow portion and deep portions, wherein the shallow portion is closer to the top surface than the deep portions, and the semiconductor layer being atop the shallow portion; a gate atop the semiconductor layer; and a source silicide region operatively coupled to the source, and a drain silicide region operatively coupled to the drain; wherein the semiconductor layer includes a source and a drain which are operatively coupled to the gate; wherein the source and the drain include respective source and drain extensions, and wherein the source and drain extensions are in contact with the shallow portion of the buried insulator layer; wherein the silicide regions are atop the shallow portion of the buried insulator layer; wherein the buried insulator layer includes transition portions between the shallow portion and the deep portions; wherein the silicide regions are atop respective of the transition portions; and wherein the silicide regions are in contact with respective of the transition portions.
Claim 28
Dependent Claim
186 words
A semiconductor-on-insulator transistor device comprising: a silicon-on-insulator substrate having a top surface, the substrate including a buried insulator layer and a semiconductor layer, the buried insulator layer having a shallow portion and deep portions, wherein the shallow portion is closer to the top surface than the deep portions, and the semiconductor layer being atop the shallow portion; a gate atop the semiconductor layer; and a source silicide region operatively coupled to the source, and a drain silicide region operatively coupled to the drain; wherein the semiconductor layer includes a source and a drain which are operatively coupled to the gate; wherein the source and the drain include respective source and drain extensions, and wherein the source and drain extensions are in contact with the shallow portion of the buried insulator layer; wherein the silicide regions are atop the shallow portion of the buried insulator layer; wherein the buried insulator layer includes transition portions between the shallow portion and the deep portions; wherein the silicide regions are atop respective of the transition portions; and wherein the silicide regions are in contact with respective of the transition portions.
Claim 29
Dependent Claim
16 words
The transistor device of claim 24 , wherein the transition portions each have a curved shape.
Claim 30
Dependent Claim
18 words
The transistor device of claim 25 , wherein the silicide regions are in contact with the shallow portion.
Claim 31
Dependent Claim
17 words
The transistor device of claim 26 , wherein the semiconductor layer includes a fully depleted channel layer.
Claim 32
Dependent Claim
16 words
The transistor device of claim 26 , wherein the buried insulator layer includes a semiconductor oxide.
References Cited (Backward Citations)
US5510640A
Cited
US5444282A
Cited
US5264395A
Cited
US6064092A
Cited
US5656844A
Cited
US5930642A
Cited
US6015752A
Cited
US5994191A
Cited
JP2000150892A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-08-19 | 2006-02-18 | 2006-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-08-19 | 2010-02-18 | 2010-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-08-19 | 2014-02-18 | 2014-08-20 | $7700.00 | Window Closed / Lapsed |