Semiconductor-on-insulator transistor having a doping profile for fully-depleted operation

Claim 2

A semiconductor-on-insulator transistor, comprising: a semiconductor substrate; a buried insulating layer disposed on said semiconductor substrate; a semiconductor film, disposed on said buried insulating layer, having a top surface, a bottom surface in contact with said buried insulating layer, a source region, and a drain region; a gate insulating layer disposed on said top surface of said semiconductor film between said source region and said drain region; a gate electrode layer disposed on said gate insulating layer; and a channel region disposed in said semiconductor film between said source region and said drain region under said gate insulating layer and on said buried insulating layer, wherein when said transistor is in the off state said channel region has a top dopant concentration in a first portion closer to said top surface of said semiconductor film, said channel region has a bottom dopant concentration in a second portion further from said top surface of said semiconductor film, and said top dopant concentration is greater than said bottom dopant concentration.

Claim 3

The transistor of claim 1 wherein said semiconductor film has a thickness between about 500 and 2,000 angstroms.

Claim 4

The transistor of claim 1 wherein said channel region is fully depleted.

Claim 5

The transistor of claim 1 further comprising a halo region disposed between said drain region and said channel region wherein said halo region has a dopant concentration greater than said bottom dopant concentration of said channel region.

Claim 6

The transistor of claim 1 wherein a doping ratio determined as said top dopant concentration divided by said bottom dopant concentration is greater than about five.

Claim 7

The transistor of claim 5 wherein said doping ratio is between about 10 and 100.

Claim 8

The transistor of claim 1 wherein said channel region has a doping profile that monotonically decreases from said top surface to said bottom surface of said semiconductor film.

Claim 9

The transistor of claim 7 wherein said doping profile substantially corresponds to a gaussian curve.

Claim 10

The transistor of claim 7 wherein said doping profile substantially corresponds to a step distribution.

Claim 11

The transistor of claim 1 wherein a threshold voltage of said transistor is greater than about 300 mV.

Claim 12

The transistor of claim 10 wherein said top dopant concentration is greater than about 8-10 16 atoms/cm 3 .

Claim 13

The transistor of claim 11 wherein said gate electrode layer is polysilicon.

Claim 14

The transistor of claim 11 wherein said gate insulating layer has a thickness of about 50 to 150 angstroms.

Claim 15

A silicon-on-insulator transistor, comprising: a silicon substrate; a buried insulating layer disposed on said silicon substrate; a silicon film with a thickness greater than about 500 angstroms, disposed on said buried insulating layer, and having a top surface, a bottom surface in contact with said buried insulating layer, a source region, and a drain region; a gate oxide layer disposed on said top surface of said silicon film between said source region and said drain region; a gate electrode layer disposed on said gate oxide layer; and a channel region disposed in said silicon film between said source region and said drain region under said gate oxide layer and on said buried insulating layer, wherein when said transistor is in the off state said channel region has a top dopant concentration in a first portion closer to said top surface of said silicon film that is sufficiently high to set a threshold voltage of said transistor of at least about 400 mV, said channel region has a bottom dopant concentration in a second portion further from said top surface of said silicon film, and said top dopant concentration is greater than said bottom dopant concentration.

Claim 16

A silicon-on-insulator transistor, comprising: a silicon substrate; a buried insulating layer disposed on said silicon substrate; a silicon film with a thickness greater than about 500 angstroms, disposed on said buried insulating layer, and having a top surface, a bottom surface in contact with said buried insulating layer, a source region, and a drain region; a gate oxide layer disposed on said top surface of said silicon film between said source region and said drain region; a gate electrode layer disposed on said gate oxide layer; and a channel region disposed in said silicon film between said source region and said drain region under said gate oxide layer and on said buried insulating layer, wherein when said transistor is in the off state said channel region has a top dopant concentration in a first portion closer to said top surface of said silicon film that is sufficiently high to set a threshold voltage of said transistor of at least about 400 mV, said channel region has a bottom dopant concentration in a second portion further from said top surface of said silicon film, and said top dopant concentration is greater than said bottom dopant concentration.

Claim 17

The transistor of claim 14 wherein said buried insulating layer is formed of a material selected from the group consisting of silicon oxide and sapphire.

Claim 18

The transistor of claim 14 wherein said channel region has a doping profile that monotonically decreases from said top surface to said bottom surface of said silicon film and a doping ratio determined as said top dopant concentration divided by said bottom dopant concentration is greater than about five.

Claim 19

The transistor of claim 16 wherein said top dopant concentration is greater than about 8×10 16 atoms/cm 3 .

Claim 20

The transistor of claim 16 wherein said silicon film has a thickness between about 500 and 2,000 angstroms.

Claim 21

The transistor of claim 14 wherein said channel region is fully depleted.

Claim 22

A semiconductor-on-insulator transistor, comprising: a semiconductor substrate; a buried insulating layer disposed on said semiconductor substrate; a semiconductor film, disposed on said buried insulating layer, having a top surface, a bottom surface in contact with said buried insulating layer, a source region, and a drain region; a gate insulating layer disposed on said top surface of said semiconductor film between said source region and said drain region; a gate electrode layer disposed on said gate insulating layer; and a channel region disposed in said semiconductor film between said source region and said drain region under said gate insulating layer and on said buried insulating layer, wherein when said transistor is in the off state said channel region has a doping profile with a peak dopant concentration closer to said top surface of said semiconductor film and a minimum dopant concentration further from said top surface of said semiconductor film, and said peak dopant concentration is greater than said minimum dopant concentration.

Claim 23

A semiconductor-on-insulator transistor, comprising: a semiconductor substrate; a buried insulating layer disposed on said semiconductor substrate; a semiconductor film, disposed on said buried insulating layer, having a top surface, a bottom surface in contact with said buried insulating layer, a source region, and a drain region; a gate insulating layer disposed on said top surface of said semiconductor film between said source region and said drain region; a gate electrode layer disposed on said gate insulating layer; and a channel region disposed in said semiconductor film between said source region and said drain region under said gate insulating layer and on said buried insulating layer, wherein when said transistor is in the off state said channel region has a doping profile with a peak dopant concentration closer to said top surface of said semiconductor film and a minimum dopant concentration further from said top surface of said semiconductor film, and said peak dopant concentration is greater than said minimum dopant concentration.

Claim 24

The transistor of claim 20 wherein a doping ratio determined as said peak dopant concentration divided by said minimum dopant concentration is greater than about two.

Claim 25

The transistor of claim 21 wherein said doping ratio is greater than about five.

Claim 26

The transistor of claim 22 wherein a threshold voltage of said transistor is greater than about 300 mV.

Claim 27

The transistor of claim 23 wherein said semiconductor film has a thickness between about 500 and 2,000 angstroms.