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US6429029B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Concurrent design and subsequent partitioning of product and test die

Assignee: FormFactor Inc
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Filing: 1998-12-31
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Granted: 2002-08-06
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Expires: 2018-12-31
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Abstract

Abstract One embodiment of the present invention concerns a design methodology for generating a test die for a product die including the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers. By partitioning the product circuitry and test circuitry into separate die, embedded test circuitry can be either eliminated or minimized on the product die. This will tend to decrease the size of the product die and decrease the cost of manufacturing the product die while maintaining a high degree of test coverage of the product circuits within the product die.

Inventors

  • 👤 Benjamin N. Eldridge
  • 👤 Igor Y. Khandros
  • 👤 David V. Pedersen
  • 👤 Ralph G. Whitten

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 12:58
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884; H; H10; H10W; H10W90/00; H10W90/701; G01R31/2886; H05; H05K; H05K3/00; H05K3/10; H05K3/20; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K3/3421; H10W72/00; H10W72/20; H10W72/251; H10W72/29; H10W72/50; H10W72/59; H10W72/90; H10W72/931; H10W72/932; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W72/952

Claims Analysis

Total Claims: 55
Claim 1
Independent Claim 86 words
A method of designing a test die for a product die, comprising: designing a test circuit and a product circuit in a unified design, the test circuit for testing during manufacture a product die into which the product circuit is integrated; partitioning the unified design into the test circuit and the product circuit; generating data for manufacture of a test die that includes the test circuit; and generating data for manufacture of the product die, wherein the test die and the product die are separate dies.
Claim 2
Independent Claim 86 words
A method of designing a test die for a product die, comprising: designing a test circuit and a product circuit in a unified design, the test circuit for testing during manufacture a product die into which the product circuit is integrated; partitioning the unified design into the test circuit and the product circuit; generating data for manufacture of a test die that includes the test circuit; and generating data for manufacture of the product die, wherein the test die and the product die are separate dies.
Claim 3
Dependent Claim 19 words
The method of claim 1 , further comprising the step of separately fabricating the test die and product die.
Claim 4
Dependent Claim 25 words
The method of claim 1 , further comprising the step of generating a description of interconnect points between the test circuit and the product circuit.
Claim 5
Dependent Claim 24 words
The method of claim 1 , further comprising the step of determining test capabilities of a host controller that communicates with the test die.
Claim 6
Dependent Claim 31 words
The method of claim 4 , further comprising the step of selecting a first test for execution by the test circuit and a second test for execution by the host controller.
Claim 7
Dependent Claim 33 words
The method of claim 1 , further comprising: determining if the partitioned test die and product die satisfy predetermined constraints; and repeating the partitioning and determining steps until the predetermined constraints are satisfied.
Claim 8
Dependent Claim 24 words
The method of claim 6 , wherein the predetermined constraints include the physical size of each of the test die and the product die.
Claim 9
Dependent Claim 23 words
The method of claim 6 , wherein the predetermined constraints include cost of manufacturing each of the test die and the product die.
Claim 10
Dependent Claim 22 words
The method of claim 6 , wherein the predetermined constraints include a selected amount of fault coverage for testing the product circuit.
Claim 11
Dependent Claim 25 words
The method of claim 6 , wherein the predetermined constraints include speed test accuracy of signals in the product die monitored by the test circuit.
Claim 12
Dependent Claim 24 words
The method of claim 6 , wherein the predetermined constraints include fabrication process parameters of each of the test die and the product die.
Claim 13
Dependent Claim 25 words
The method of claim 6 , wherein the predetermined constraints include AC timing parameters of signals in the product die monitored by the test circuit.
Claim 14
Dependent Claim 23 words
The method of claim 6 , wherein the determining step further comprises simulating a partition of the test die and the product die.
Claim 15
Dependent Claim 36 words
The method of claim 6 , further comprising the step of generating a number of interconnection points on the test die and the product die, and wherein the predetermined constraints include the number of interconnection points.
Claim 16
Dependent Claim 13 words
The method of claim 1 , further including designing a second test circuit.
Claim 17
Dependent Claim 21 words
The method of claim 15 , further including generating data for manufacture of the second test circuit on the product die.
Claim 18
Dependent Claim 15 words
The method of claim 16 , wherein the second circuit comprises Built-In Self-Test (BIST) circuitry.
Claim 19
Dependent Claim 13 words
The method of claim 16 , wherein the second circuit comprises SCAN circuitry.
Claim 20
Dependent Claim 24 words
The method of claim 1 , wherein the test circuit is capable of testing a plurality of product die each having the product circuit.
Claim 21
Dependent Claim 12 words
The method of claim 1 , further comprising adjusting the test circuit.
Claim 22
Dependent Claim 17 words
The method of claim 20 , wherein the adjusting comprises adding additional circuitry to the test circuit.
Claim 23
Dependent Claim 17 words
The method of claim 20 , wherein the adjusting further comprises removing some of the test circuit.
Claim 24
Dependent Claim 20 words
The method of claim 1 , further comprising the step of adding Built-In Self-Test (BIST) circuitry to the product die.
Claim 25
Independent Claim 103 words
A method of designing a test die and a product die, comprising: designing a plurality of test circuits and a plurality of product circuits in a unified design, the test circuits for communicating with the product circuits; partitioning the unified design into the plurality of test circuits and the plurality of product circuits; generating data for manufacturing at least one test die that includes the plurality of test circuits; and generating data for manufacturing at least one product die that includes the plurality of product circuits, wherein the at least one test die and the at least one product die are separate dies.
Claim 26
Independent Claim 103 words
A method of designing a test die and a product die, comprising: designing a plurality of test circuits and a plurality of product circuits in a unified design, the test circuits for communicating with the product circuits; partitioning the unified design into the plurality of test circuits and the plurality of product circuits; generating data for manufacturing at least one test die that includes the plurality of test circuits; and generating data for manufacturing at least one product die that includes the plurality of product circuits, wherein the at least one test die and the at least one product die are separate dies.
Claim 27
Dependent Claim 13 words
The method of claim 24 , wherein each test circuit comprises unique circuitry.
Claim 28
Dependent Claim 25 words
The method of claim 24 , wherein one of the plurality of test circuits includes test circuitry commonly used by all of the test circuits.
Claim 29
Dependent Claim 16 words
The method of claim 26 , wherein the commonly used test circuitry comprises a pattern generator.
Claim 30
Dependent Claim 17 words
The method of claim 26 , wherein the commonly used test circuitry communicates with a host controller.
Claim 31
Dependent Claim 29 words
The method of claim 24 , further comprising the step of fabricating the at least one test die and the at least one product die on separate semiconductor wafers.
Claim 32
Dependent Claim 39 words
The method of claim 24 , further comprising: determining if the at least one test die and the at least one product die satisfy predetermined constraints; and repeating the partitioning and determining steps until the predetermined constraints are satisfied.
Claim 33
Independent Claim 50 words
A method of producing a tester, comprising: generating a product circuit and test circuit, wherein the test circuit includes circuitry for testing the product circuit; partitioning circuitry between the product circuit and the test circuit; evaluating the partition; and fabricating the product circuit and the test circuit on different dies.
Claim 34
Independent Claim 50 words
A method of producing a tester, comprising: generating a product circuit and test circuit, wherein the test circuit includes circuitry for testing the product circuit; partitioning circuitry between the product circuit and the test circuit; evaluating the partition; and fabricating the product circuit and the test circuit on different dies.
Claim 35
Dependent Claim 20 words
The method of claim 31 , wherein the partitioning step and evaluating steps are repeated until predetermined constraints are satisfied.
Claim 36
Dependent Claim 67 words
A test die for testing product circuitry of a separate product die, the test die comprising: test circuitry generated by: (i) concurrently designing the test circuitry and the product circuitry into a unified design, (ii) partitioning the test circuitry from the product circuitry, and (iii) fabricating the test circuitry into the test die, which is separate from the product die into which the product circuitry is fabricated.
Claim 37
Dependent Claim 67 words
A test die for testing product circuitry of a separate product die, the test die comprising: test circuitry generated by: (i) concurrently designing the test circuitry and the product circuitry into a unified design, (ii) partitioning the test circuitry from the product circuitry, and (iii) fabricating the test circuitry into the test die, which is separate from the product die into which the product circuitry is fabricated.
Claim 38
Dependent Claim 40 words
The test die of claim 33 , wherein the test die is further generated by: determining if the test circuitry satisfies predetermined constraints; and iteratively repartitioning the unified design and performing the determining step until the predetermined constraints are satisfied.
Claim 39
Dependent Claim 18 words
The test die of claim 33 , further comprising a plurality of pads coupled to the test circuitry.
Claim 40
Dependent Claim 24 words
The test die of claim 35 , wherein the plurality of pads comprise: bond pads; and special contact pads for receiving spring contact elements.
Claim 41
Dependent Claim 18 words
The test die of claim 36 , wherein the bond pads and special contact pads have different heights.
Claim 42
Dependent Claim 25 words
The test die of claim 35 , further comprising contact elements coupled to the pads and electrically coupling the test circuitry and the product circuitry.
Claim 43
Dependent Claim 14 words
The test die of claim 38 , wherein the contact elements have different heights.
Claim 44
Dependent Claim 17 words
The test die of claim 38 , wherein the plurality of contact elements comprise spring contact elements.
Claim 45
Dependent Claim 16 words
The test die of claim 38 , wherein the plurality of contact elements comprise contact balls.
Claim 46
Dependent Claim 21 words
The test die of claim 33 , wherein the test circuitry is configured to test AC parametrics of the product circuitry.
Claim 47
Dependent Claim 21 words
The test die of claim 33 , wherein the test circuitry is configured to test DC parametrics of the product circuitry.
Claim 48
Dependent Claim 18 words
The test die of claim 33 , wherein the test circuitry is configured to program the product circuitry.
Claim 49
Dependent Claim 21 words
The test die of claim 33 , wherein the test circuitry is configured to enable redundant circuitry of the product circuitry.
Claim 50
Independent Claim 95 words
A medium readable by a computing device, the medium storing a sequence of instructions for generating a description of a test die and a description of a product die, wherein the instructions cause the computing device to: generate a unified circuit design including product circuitry and test circuitry for testing said product circuitry; and partition the unified circuit design into separate descriptions of the test circuitry to be integrated into a test die and the product circuitry to be integrated into a product die, wherein the test die and the product die are separate dies.
Claim 51
Independent Claim 95 words
A medium readable by a computing device, the medium storing a sequence of instructions for generating a description of a test die and a description of a product die, wherein the instructions cause the computing device to: generate a unified circuit design including product circuitry and test circuitry for testing said product circuitry; and partition the unified circuit design into separate descriptions of the test circuitry to be integrated into a test die and the product circuitry to be integrated into a product die, wherein the test die and the product die are separate dies.
Claim 52
Dependent Claim 51 words
The medium of claim 46 , wherein the instructions cause the computing device to further: determine if the descriptions of the test circuitry and product circuitry satisfy predetermined constraints; and repartition the unified circuit design into updated descriptions of the test circuitry and product circuitry until the predetermined constraints are satisfied.
Claim 53
Independent Claim 73 words
A method of designing a product die for a test die, comprising: designing a product circuit to be tested by a predetermined test circuit, the product circuit and test circuit incorporated into a unified design; and partitioning the unified design into the test circuit to be integrated into a test die and the product circuit to be integrated into a product die, wherein the test die and the product die are separate dies.
Claim 54
Independent Claim 73 words
A method of designing a product die for a test die, comprising: designing a product circuit to be tested by a predetermined test circuit, the product circuit and test circuit incorporated into a unified design; and partitioning the unified design into the test circuit to be integrated into a test die and the product circuit to be integrated into a product die, wherein the test die and the product die are separate dies.
Claim 55
Dependent Claim 19 words
The method of claim 48 , further comprising the step of separately fabricating the product die and test die.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2005-08-05 2006-02-04 2006-08-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2009-08-05 2010-02-04 2010-08-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2013-08-05 2014-02-04 2014-08-06 $7700.00 Window Closed / Lapsed

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