EP0855651A2
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Method of design for testability and method of test sequence generation
Assignee: Panasonic Holdings Corp
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Filing: 1998-01-15
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Granted: —
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Expires: 2018-01-15
Abstract
Abstract The invention provides a method of design for testability at RTL which can guarantee high fault coverage and a method of test sequence generation for easily generating test sequences for an RTL circuit which is designed to be easily testable by the method of design for testability. In the RTL circuit, scannable registers are selected so that the RTL circuit can attain an easily testable circuit structure such as an acyclic structure. This RTL circuit is timeframe expanded on the basis of a predetermined evaluation function and logically synthesized, so as to generate a timeframe expanded combinational circuit, that is, a gate level timeframe expanded circuit, as a circuit for test sequence generation. For the timeframe expanded combinational circuit, test patterns for multiple stuck-at faults are generated, the test patterns are transformed into test sequences on the basis of data on timeframes including primary inputs and pseudo-primary inputs, and the test sequences are transformed into scanning test sequences in view of a scan shift operation.
Inventors
- 👤 Toshinori Hosokawa
- 👤 Tomoo Inoue
- 👤 Hideo Fujiwara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 10:51
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/318583; G01R31/318586; G01R31/318594; G01R31/3183; G01R31/318392
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
97 words
A method of design for testability for modifying design
of an RTL circuit, that is, an integrated circuit designed at
register transfer level, so as to attain testability after
manufacture, comprising: a first step of specifying an easily testable circuit
structure; and a second step of selecting scannable registers among
registers included in said RTL circuit so that said RTL circuit
in test has said easily testable circuit structure specified in
said first step in assuming a normal data input of a scannable
register as a pseudo-primary output and a data output thereof
as a pseudo-primary input.
Claim 2
Dependent Claim
28 words
The method of design for testability of Claim 1, wherein said easily testable circuit structure specified
in said first step is an acyclic structure including no
feedback loops.
Claim 3
Dependent Claim
31 words
The method of design for testability of Claim 1, wherein said easily testable circuit structure specified
in said first step is an n-fold line-up structure, wherein n is
a natural number.
Claim 4
Dependent Claim
29 words
The method of design for testability of Claim 1, wherein said easily testable circuit structure specified
in said first step is a structure having combinational test
pattern generation complexity.
Claim 5
Dependent Claim
51 words
The method of design for testability of Claim 1, wherein said easily testable circuit structure specified
in said first step is an n-fold acyclic structure in which each
of paths from primary or pseudo-primary inputs to primary or
pseudo-primary outputs contains n or less registers, wherein n
is a natural number.
Claim 6
Dependent Claim
53 words
The method of design for testability of Claim 1, wherein said easily testable circuit structure specified
in said first step is a structure in which each of paths from
primary or pseudo-primary inputs to primary or pseudo-primary
outputs contains n or less stages of gates, wherein n is 0 or
a natural number.
Claim 7
Dependent Claim
75 words
The method of design for testability of Claim 1,
further comprising a third step of additionally selecting
scannable registers so that paths from one pseudo-primary input
to primary or pseudo-primary outputs contain the same number of
registers in assuming a normal data input of a scannable
register as a pseudo-primary output and a data output thereof
as a pseudo-primary input in said RTL circuit in which said
scannable registers are selected in said second step.
Claim 8
Dependent Claim
110 words
The method of design for testability of Claim 1, wherein said second step includes: a first process for partitioning said RTL circuit
into plural blocks; a second process for selecting, in each of said
blocks, registers reachable in a direction from an output to an
input of said block by passing merely through combinational
facilities as said scannable registers; and a third process for selecting said scannable
registers among said registers of said RTL circuit so that each
block in test attains said easily testable circuit structure in
assuming a normal data input of a scannable register as a
pseudo-primary output and a data output thereof as a pseudo-primary
input.
Claim 9
Independent Claim
158 words
A method of test sequence generation for an RTL
circuit, that is, an integrated circuit designed at register
transfer level, said RTL circuit having an acyclic structure in
test or having a structure in which scannable registers are
selected and an acyclic structure is attained in test in
assuming a normal data input of a scannable register as a
pseudo-primary output and a data output thereof as a pseudo-primary
input, comprising: a first step of converting said RTL circuit into a
timeframe expanded combinational circuit, that is, a gate level
timeframe expanded circuit; a second step of generating test patterns for said
timeframe expanded combinational circuit generated in said
first step; and a third step of transforming said test patterns generated
in said second step into test sequences for the sequential
circuit on the basis of data on timeframes including each of
primary inputs and pseudo-primary inputs of said timeframe
expanded combinational circuit generated in said first step.
Claim 10
Dependent Claim
92 words
The method of test sequence generation of Claim 9, wherein said first step includes: an RTL timeframe expanding process for timeframe
expanding said RTL circuit on the basis of a predetermined
evaluation function; a logic synthesizing process for converting said RTL
circuit into a gate level circuit through logic synthesis;
and a test sequence generation circuit generating process
for generating said timeframe expanded combinational circuit on
the basis of the timeframe expanded RTL circuit obtained in
said RTL timeframe expanding process and the gate level circuit
generating in said logic synthesizing process.
Claim 11
Dependent Claim
61 words
The method of test sequence generation of Claim 10, wherein, in said RTL timeframe expanding process, said RTL
circuit is timeframe expanded by using a total number of
combinational facilities included in each timeframe or the
total of the numbers of gates estimated for the combinational
facilities in each timeframe as said predetermined evaluation
function, with minimizing said predetermined evaluation
function.
Claim 12
Dependent Claim
47 words
The method of test sequence generation of Claim 10, wherein, in said RTL timeframe expanding process, said RTL
circuit is timeframe expanded by using a number of timeframes
including a pseudo-primary input or a pseudo-primary output as
said predetermined evaluation function, with minimizing said
predetermined evaluation function.
Claim 13
Dependent Claim
88 words
The method of test sequence generation of Claim 10, wherein, in said RTL timeframe expanding process, said RTL
circuit is timeframe expanded by using, as said predetermined
evaluation function, a value obtained by subtracting a number
of registers each of which the pseudo-primary input
corresponding thereto is included in a timeframe following a
timeframe including its corresponding pseudo-primary output
from a sum of a total number of timeframes including each
pseudo-primary input and a total number of timeframes including
each pseudo-primary output, with minimizing said predetermined
evaluation function.
Claim 14
Dependent Claim
45 words
The method of test sequence generation of Claim 10, wherein, in said RTL timeframe expanding process, said RTL
circuit is timeframe expanded by using a total number of
primary inputs included in each timeframe as said predetermined
evaluation function, with maximizing said predetermined
evaluation function.
Claim 15
Dependent Claim
133 words
The method of test sequence generation of Claim 10, wherein said RTL timeframe expanding process includes: a first process for obtaining a maximum sequential
depth of each of primary outputs and pseudo-primary outputs of
said RTL circuit; a second process for sorting said primary outputs and
pseudo-primary outputs of said RTL circuit in a descending
order of said maximum sequential depths thereof obtained in
said first process; a third process for setting a value obtained by
adding one to the maximum value of said maximum sequential
depth obtained in said first process as a number of timeframes
in timeframe expansion; and a fourth process for conducting timeframe expansion
with respect to said primary outputs and pseudo-primary outputs
in accordance with said predetermined evaluation function in
the sorted order obtained in said second process.
Claim 16
Dependent Claim
84 words
The method of test sequence generation of Claim 10, wherein said first step includes a pre-process for
grouping, in said RTL circuit, combinational facilities
containing none of registers, primary inputs and primary
outputs in a path therebetween, in said RTL timeframe expanding process, the timeframe
expansion is conducted with said combinational facilities
grouped in said pre-process regarded as one combinational
facility, and in said logic synthesizing process, the logic synthesis is
conducted by using said combinational facilities grouped in
said pre-process as one unit.
Claim 17
Dependent Claim
60 words
The method of test sequence generation of Claim 9, wherein said first step includes: a logic synthesizing process for logically
synthesizing said RTL circuit; and a gate level timeframe expanding process for
generating said timeframe expanded combinational circuit
through timeframe expansion of said gate level circuit
generated in said logic synthesizing process on the basis of
said predetermined evaluation function.
Claim 18
Dependent Claim
46 words
The method of test sequence generation of Claim 17, wherein, in said gate level timeframe expanding process,
said gate level circuit is timeframe expanded by using a total
number of gates included in each timeframe as said
predetermined evaluation function, with minimizing said
predetermined evaluation function.
Claim 19
Dependent Claim
60 words
The method of test sequence generation of Claim 9, wherein, in said third step, said test patterns are
transformed into said test sequences with one scan path formed
by using scan FFs composing a register corresponding to a
pseudo-primary output included in one timeframe and scan FFs
composing a register corresponding to a pseudo-primary input
included in another following timeframe.
References Cited (Backward Citations)
No citation records indexed.
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