Fault detection in integrated circuit chips and in circuit cards and systems including such chips

Abstract

Abstract VLSI chips contain a very high density of logic elements and have only a limited number of pin connections making complete testing by conventional means impracticable. The invention provides a self-verifying chip. The chip includes a data processing chain (10) and a plurality of fault detecting circuits (13,14,15) coupled to the data processing chain. A plurality of internal stimulus generators (18,19,20) generate test signal patterns in response to a supervisory control (21) which are applied to intermediate points of the data processing chain. Outputs from the fault detecting circuits (13,14,15) are applied to an error status generator (16) which provides error signals indicating fault conditions at various points of the data processing chain. Fault detecting circuits (18A.21A) may also monitor the internal stimulus generators and the supervisory control means. The devices of the data processing chain may normally operate in a parallel-load mode, but may be loaded with the test signal patterns in serial mode. The chip may include duplicate functional or complementary logic for the data processing chain, and the fault detecting circuits may be arranged to check the operation of the two logic chains against each other. A number of chips according to the invention may be mounted on a card, with a card fault detector receiving the outputs of the error status generators of the chips and providing an output indicating the faults detected in the chips and in the card wiring, and, in turn, in a complete system the outputs of the card fault detectors may be applied to a system fault generator monitoring the occurrence of faults in the whole system.

Inventors

• 👤 Richard Milan Sedmak

Bibliographic Details