Through-chip conductors for low inductance chip-to-chip integration and off-chip connections

Claim 1

A method of electrically and thermally connecting a semiconductor device having a front surface with active devices and a back surface to a different level of packaging, comprising: (a) providing at least one first through-chip conductor and at least one second through-chip conductor; (b) electrically passing a first characteristic through the first through-chip conductor, from said active devices of said semiconductor device to said different level of packaging, wherein the first characteristic comprises an electrical/physical characteristic; and (c) passing a second characteristic through the second through-chip conductor to said back surface of said semiconductor device, wherein the second characteristic comprises a thermal characteristic; wherein said step b) further comprises the steps of: b1) providing at least one chip connector; and b2) electrically connecting said active devices of said semiconductor device to said different level of packaging with said chip connector; wherein said step b1) further comprises: 1) depositing a first sacrificial layer on said semiconductor device; 2) etching a pair of first via holes in said first sacrificial layer; 3) plating a first conductive material in at least one of said first via holes; 4) depositing a second sacrificial layer on said first sacrificial layer; 5) etching a second via hole in said second sacrificial layer, wherein said second via hole connects with at least one of said first via holes; 6) plating a second conductive material in said second via hole, and said first via hole connected therewith; and 7) removing said first and second sacrificial layer.

Claim 2

A method of electrically and thermally connecting a semiconductor device having a front surface with active devices and a back surface to a different level of packaging, comprising: (a) providing at least one first through-chip conductor and at least one second through-chip conductor; (b) electrically passing a first characteristic through the first through-chip conductor, from said active devices of said semiconductor device to said different level of packaging, wherein the first characteristic comprises an electrical/physical characteristic; and (c) passing a second characteristic through the second through-chip conductor to said back surface of said semiconductor device, wherein the second characteristic comprises a thermal characteristic; wherein said step b) further comprises the steps of: b1) providing at least one chip connector; and b2) electrically connecting said active devices of said semiconductor device to said different level of packaging with said chip connector; wherein said step b1) further comprises: 1) depositing a first sacrificial layer on said semiconductor device; 2) etching a pair of first via holes in said first sacrificial layer; 3) plating a first conductive material in at least one of said first via holes; 4) depositing a second sacrificial layer on said first sacrificial layer; 5) etching a second via hole in said second sacrificial layer, wherein said second via hole connects with at least one of said first via holes; 6) plating a second conductive material in said second via hole, and said first via hole connected therewith; and 7) removing said first and second sacrificial layer.

Claim 6

A method of fabricating a pair of chip connectors for a semiconductor device, comprising: a) depositing a first sacrificial layer on said semiconductor device; b) etching a first via hole in said first sacrificial layer; c) plating a first conductive material in said first via hole; d) depositing a second sacrificial layer on said first sacrificial layer; e) etching a second via hole in said second sacrificial layer and said first sacrificial layer; f) plating a second conductive material in said second via hole; and g) removing said first and second sacrificial layer.

Claim 7

A method of fabricating a pair of chip connectors for a semiconductor device, comprising: a) depositing a first sacrificial layer on said semiconductor device; b) etching a first via hole in said first sacrificial layer; c) plating a first conductive material in said first via hole; d) depositing a second sacrificial layer on said first sacrificial layer; e) etching a second via hole in said second sacrificial layer and said first sacrificial layer; f) plating a second conductive material in said second via hole; and g) removing said first and second sacrificial layer.