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US5401672A Expired / Lapsed US ⏱️ 0.0 years remaining

Process of bonding semiconductor wafers having conductive semiconductor material extending through each wafer at the bond areas

Assignee: Kulite Semiconductor Products Inc
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Filing: 1994-08-17
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Granted: 1995-03-28
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Expires: 2014-08-17
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Abstract

Abstract A process wherein plurality of individual device layers having semiconductor material conductive regions extending therethrough are bonded together before or after one or more circuit elements have been fabricated on each layer. Groups of device layers are formed by electrochemically anodizing a wafer of semiconductor material. The wafer is rendered totally porous except for a series of non-porous regions extending therethrough. The wafer is then oxidized and densifted to result in a wafer having a plurality of electrically isolated extended contacts. A plurality of wafers are processed in this manner. A variety of integrated circuit devices are then formed on the surface of each wafer. Once the processing of all individual wafers is completed, each wafer is bonded to another, with the extending contact aligned to electrically interconnect each device layer. The wafers are then diced to provide a plurality of multi-level integrated circuit structures.

Inventors

  • 👤 Anthony D. Kurtz
  • 👤 Alexander A. Ned

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 07:22
CPC Classifications
H; H10; H10W; H10W90/00; H10W20/00; H10W20/20; H10W90/20; H10W90/297; Y; Y10; Y10S; Y10S148/00; Y10S148/012

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 91 words
A method for fabricating a semiconductor structure comprising the steps of: providing a first wafer having an electrically isolated, first conductive region of semiconductor material extending between opposed surfaces thereof; providing a second wafer having an electrically isolated, second conductive region of semiconductor material extending between opposed surfaces thereof; and bonding said second wafer to said first wafer such that a contact surface of said first conductive region is coupled to a contact surface of said second conductive region, thereby defining an isolated conducting path through said first and second wafers.
Claim 2
Independent Claim 91 words
A method for fabricating a semiconductor structure comprising the steps of: providing a first wafer having an electrically isolated, first conductive region of semiconductor material extending between opposed surfaces thereof; providing a second wafer having an electrically isolated, second conductive region of semiconductor material extending between opposed surfaces thereof; and bonding said second wafer to said first wafer such that a contact surface of said first conductive region is coupled to a contact surface of said second conductive region, thereby defining an isolated conducting path through said first and second wafers.
Claim 3
Dependent Claim 27 words
A method according to claim 1, further comprising fabricating at least one circuit element on a surface of at least one of said first and second wafers.
Claim 4
Dependent Claim 16 words
A method according to claim 2, wherein said fabricating step is performed after said bonding step.
Claim 5
Dependent Claim 21 words
A method according to claim 2, wherein a first circuit element is fabricated on said first wafer during said fabricating step.
Claim 6
Dependent Claim 23 words
A method according to claim 4, further comprising defining a cavity on surface of said second wafer for accommodating said first circuit element.
Claim 7
Dependent Claim 16 words
A method according to claim 5, wherein said cavity is hermetically sealed during said bonding step.
Claim 8
Dependent Claim 21 words
A method according to claim 5, wherein a second circuit element is fabricated on said second wafer during said fabricating step.
Claim 9
Dependent Claim 31 words
A method according to claim 7, further comprising the step of bonding a third wafer to said second wafer, said third wafer defining a cavity for receiving said second circuit element.
Claim 10
Dependent Claim 15 words
A method according to claim 1, wherein said conductive regions are formed from monocrystalline silicon.
Claim 11
Dependent Claim 35 words
A method according to claim 1, further comprising the step of bonding a third wafer having a region of semiconductor material extending therethrough to said second wafer, thereby electrically interconnecting said first and third wafers.

References Cited (Backward Citations)

US4786954A Cited
US4972248A Cited
US5298767A Cited
US5286671A Cited
US5666833A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-03-27 1998-09-26 1999-03-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-03-27 2002-09-26 2003-03-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-03-27 2006-09-26 2007-03-28 $7700.00 Window Closed / Lapsed

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