Damascene process for MOSFET fabrication

Claim 1

A method for fabricating an integrated circuit, the method comprising: forming a first dielectric layer over a first surface of a semiconductor region; etching through the thickness of a part of said first dielectric layer, said semiconductor region acting as an etch stop whereby said etched-through first dielectric layer bounds a limited area of said semiconductor region at but not extending into said first surface; forming a second dielectric layer upon said first dielectric layer, said second dielectric layer covering said first surface; forming a conductive layer upon said second dielectric layer; removing said conductive layer and said second dielectric layer in all areas of said first surface except over said limited area; and removing remaining portions of said first dielectric layer, leaving said conductive layer and said second dielectric layer over said limited area of said semiconductor region.

Claim 2

A method for fabricating an integrated circuit, the method comprising: forming a first dielectric layer over a first surface of a semiconductor region; etching through the thickness of a part of said first dielectric layer, said semiconductor region acting as an etch stop whereby said etched-through first dielectric layer bounds a limited area of said semiconductor region at but not extending into said first surface; forming a second dielectric layer upon said first dielectric layer, said second dielectric layer covering said first surface; forming a conductive layer upon said second dielectric layer; removing said conductive layer and said second dielectric layer in all areas of said first surface except over said limited area; and removing remaining portions of said first dielectric layer, leaving said conductive layer and said second dielectric layer over said limited area of said semiconductor region.

Claim 10

A method for fabricating an integrated circuit, the method comprising: forming a first dielectric layer over a first surface of a semiconductor region; forming a second dielectric layer upon said first dielectric layer; etching through the thicknesses of a region of said second dielectric layer and an aligned region of said first dielectric layer, said semiconductor region functioning as an etch stop, to define at least one exposed area of said semiconductor region at but not extending into said first surface, said exposed area defined by the etched-through regions of said first and second dielectric layers; forming a third dielectric layer over said first surface to form a dielectric over said exposed area; forming a conductive layer over said third dielectric layer; removing portions of said conductive layer and said third dielectric layer in regions above remaining portions of said first and second dielectric layers, the removing leaving a portion of the conductive layer and the third dielectric over said exposed area.

Claim 11

A method for fabricating an integrated circuit, the method comprising: forming a first dielectric layer over a first surface of a semiconductor region; forming a second dielectric layer upon said first dielectric layer; etching through the thicknesses of a region of said second dielectric layer and an aligned region of said first dielectric layer, said semiconductor region functioning as an etch stop, to define at least one exposed area of said semiconductor region at but not extending into said first surface, said exposed area defined by the etched-through regions of said first and second dielectric layers; forming a third dielectric layer over said first surface to form a dielectric over said exposed area; forming a conductive layer over said third dielectric layer; removing portions of said conductive layer and said third dielectric layer in regions above remaining portions of said first and second dielectric layers, the removing leaving a portion of the conductive layer and the third dielectric over said exposed area.

Claim 16

A method of forming a MOS transistor, the method comprising: forming a sacrificial dielectric layer over a first surface of a semiconductor region; etching through the thickness of a portion of the sacrificial layer over part of said first surface of the semiconductor region, said part of said first surface acting as an etch stop to expose a gate region area at but not extending into said first surface; forming a gate dielectric over a remaining portion of the sacrificial layer and over said gate region area; forming a conductive layer over the gate dielectric; performing a chemical-mechanical polish to remove portions of the gate dielectric and the conductive layer from over the remaining portion of the sacrificial layer, thereby defining a gate electrode and an underlying gate dielectric layer over said gate region; removing the remaining portion of the sacrificial layer; subsequently forming source and drain regions in the semiconductor region adjacent said gate region area using said gate electrode as a self-alignment mask.

Claim 17

A method of forming a MOS transistor, the method comprising: forming a sacrificial dielectric layer over a first surface of a semiconductor region; etching through the thickness of a portion of the sacrificial layer over part of said first surface of the semiconductor region, said part of said first surface acting as an etch stop to expose a gate region area at but not extending into said first surface; forming a gate dielectric over a remaining portion of the sacrificial layer and over said gate region area; forming a conductive layer over the gate dielectric; performing a chemical-mechanical polish to remove portions of the gate dielectric and the conductive layer from over the remaining portion of the sacrificial layer, thereby defining a gate electrode and an underlying gate dielectric layer over said gate region; removing the remaining portion of the sacrificial layer; subsequently forming source and drain regions in the semiconductor region adjacent said gate region area using said gate electrode as a self-alignment mask.

Claim 27

A method of forming a MOS transistor, the method comprising: forming a sacrificial dielectric layer over a first surface of a semiconductor region; etching through the thickness of a portion of the sacrificial layer over part of said first surface of the semiconductor region, said part of said first surface acting as an etch stop to expose a gate region area at but not extending into said first surface; forming a gate dielectric over a remaining portion of the sacrificial layer and over said gate region area, said gate dielectric having a dielectric constant greater than that of silicon dioxide; forming a refractory metal or refractory metal silicide conductive layer over the gate dielectric; performing a chemical-mechanical polish to remove portions of the gate dielectric and the conductive layer from over the remaining portion of the sacrificial layer, thereby defining a gate electrode and an underlying gate dielectric layer over said gate region area; removing the remaining portion of the sacrificial layer; subsequently ion implanting lightly doped source and drain regions in the semiconductor region adjacent to sides of said gate region area using said gate electrode as a self-alignment mask; forming sidewall insulators along sidewalls of the gate electrode; and ion implanting more heavily doped regions in the lightly doped source and drain regions, using said sidewall insulators as an implant mask.

Claim 28

A method of forming a MOS transistor, the method comprising: forming a sacrificial dielectric layer over a first surface of a semiconductor region; etching through the thickness of a portion of the sacrificial layer over part of said first surface of the semiconductor region, said part of said first surface acting as an etch stop to expose a gate region area at but not extending into said first surface; forming a gate dielectric over a remaining portion of the sacrificial layer and over said gate region area, said gate dielectric having a dielectric constant greater than that of silicon dioxide; forming a refractory metal or refractory metal silicide conductive layer over the gate dielectric; performing a chemical-mechanical polish to remove portions of the gate dielectric and the conductive layer from over the remaining portion of the sacrificial layer, thereby defining a gate electrode and an underlying gate dielectric layer over said gate region area; removing the remaining portion of the sacrificial layer; subsequently ion implanting lightly doped source and drain regions in the semiconductor region adjacent to sides of said gate region area using said gate electrode as a self-alignment mask; forming sidewall insulators along sidewalls of the gate electrode; and ion implanting more heavily doped regions in the lightly doped source and drain regions, using said sidewall insulators as an implant mask.