Semiconductor device having two-level wiring

Claim 1

A semiconductor integrated circuit comprising a P-channel field effect transistor having a first gate, an N-channel field effect transistor having a second gate, and an insulating layer extending over both of said first and second gates, wherein said first gate comprises a first gate insulating film contacting a region between source and drain regions of said P-channel transistor, a first semiconductor layer of a first conductivity type over said first gate insulating film and a first metal layer over said first semiconductor layer, and said second gate comprises a second gate insulating film contacting a region between source and drain regions of said N-channel transistor, a second semiconductor layer of a second conductivity type opposite to said first conductivity type over said second gate insulating film and a second metal layer over said second semiconductor layer, and wherein said first semiconductor layer directly contacts said second semiconductor layer, and said first and second metal layers form a common metal layer directly contacting said first and second semiconductor layers.