High dielectric constant gate dielectric integrated with nitrogenated gate electrode

Claim 2

A semiconductor process for forming a gate electrode of an MOS transistor, said process comprising: depositing a gate dielectric layer on an upper surface of a semiconductor substrate, wherein a dielectric constant of said gate dielectric layer is in the range of approximately 25 to 300 and wherein a thickness of said gate dielectric is in the range of approximately 50 to 1000 angstroms; forming a conductive gate layer on said gate dielectric layer; introducing a first nitrogen distribution into said gate dielectric layer by implanting a first nitrogen bearing implant species into said gate dielectric layer using a first implant energy and a first implant dose, wherein a peak impurity concentration of said first nitrogen distribution resides approximately at a depth of an interface between said semiconductor substrate and said gate dielectric layer; and introducing a second nitrogen distribution into said gate dielectric layer by implanting a second nitrogen bearing impurity distribution into said gate dielectric layer using a second implant energy and a second implant dose, wherein a peak impurity concentration of said second nitrogen distribution resides approximately at a depth of an interface between said gate dielectric layer and said conductive gate layer.

Claim 3

The process of claim 1, wherein said gate dielectric layer comprises an oxide selected from the group comprising Be x O y , Mg x O y , ZrO 2 , Ca x O y , TiO 2 and Ta 2 O 5 .

Claim 4

The process of claim 2, wherein the step of depositing said gate dielectric comprises immersing said semiconductor substrate in a CVD reactor chamber comprising an oxygen bearing ambient maintained at a temperature of approximately 200 to 900° C. and a pressure of less than approximately 2 torrs.

Claim 5

The process of claim 1, wherein the step of forming said conductive gate layer comprises depositing a polysilicon layer by thermally decomposing silane in a CVD reactor chamber maintained at a temperature in the range of approximately 580 to 650° C. and a pressure of less than approximately 2 torrs.

Claim 6

The process of claim 4, wherein the step of forming said conductive gate layer further comprises introducing a gate impurity distribution into said polysilicon layer wherein a concentration of said gate impurity distribution is sufficient to reduce a sheet resistivity of said polysilicon to less than approximately 50 Ω/square.

Claim 7

The process of claim 1, wherein said first implant energy is in the range of approximately 50 to 1000 keV and said first implant dose is in the range of approximately 1×10 13 to 5×10 15 atoms/cm 2 .

Claim 8

The process of claim 1, wherein said second implant energy is in the range of approximately 50 to 1000 keV and said second implant dose is in the range of approximately 1×10 13 to 5×10 15 atoms/cm 2 , and further wherein said second implant energy is less than said first implant energy.

Claim 9

A process for fabricating an MOS transistor, said process comprising: depositing a gate dielectric layer on an upper surface of a semiconductor substrate, wherein a dielectric constant of said gate dielectric layer is in the range of approximately 40 to 150 and wherein a thickness of said gate dielectric is in the range of approximately 50 to 1000 angstroms; forming a conductive gate layer on said gate dielectric layer; introducing a first nitrogen distribution into said gate dielectric layer by implanting a first nitrogen bearing implant species into said gate dielectric layer using a first implant energy and a first implant dose, wherein a peak impurity concentration of said first nitrogen distribution resides approximately at a depth of an interface between said semiconductor substrate and said gate dielectric layer; introducing a second nitrogen distribution into said gate dielectric layer by implanting a second nitrogen bearing impurity distribution into said gate dielectric layer using a second implant energy and a second implant dose, wherein a peak impurity concentration of said second nitrogen distribution resides approximately at a depth of an interface between said gate dielectric layer and said conductive gate layer; patterning said gate dielectric layer to form a gate electrode, wherein said gate electrode is aligned over a channel region of said semiconductor substrate; implanting at least one source/drain impurity distribution into source/drain regions located within said semiconductor substrate laterally displaced on either side of said channel region; and annealing said semiconductor substrate in an inert ambient maintained at a temperature in excess of approximately 500° C. to activate said source/drain impurity distribution.

Claim 10

A process for fabricating an MOS transistor, said process comprising: depositing a gate dielectric layer on an upper surface of a semiconductor substrate, wherein a dielectric constant of said gate dielectric layer is in the range of approximately 40 to 150 and wherein a thickness of said gate dielectric is in the range of approximately 50 to 1000 angstroms; forming a conductive gate layer on said gate dielectric layer; introducing a first nitrogen distribution into said gate dielectric layer by implanting a first nitrogen bearing implant species into said gate dielectric layer using a first implant energy and a first implant dose, wherein a peak impurity concentration of said first nitrogen distribution resides approximately at a depth of an interface between said semiconductor substrate and said gate dielectric layer; introducing a second nitrogen distribution into said gate dielectric layer by implanting a second nitrogen bearing impurity distribution into said gate dielectric layer using a second implant energy and a second implant dose, wherein a peak impurity concentration of said second nitrogen distribution resides approximately at a depth of an interface between said gate dielectric layer and said conductive gate layer; patterning said gate dielectric layer to form a gate electrode, wherein said gate electrode is aligned over a channel region of said semiconductor substrate; implanting at least one source/drain impurity distribution into source/drain regions located within said semiconductor substrate laterally displaced on either side of said channel region; and annealing said semiconductor substrate in an inert ambient maintained at a temperature in excess of approximately 500° C. to activate said source/drain impurity distribution.

Claim 11

The process of claim 8, wherein a lateral dimension of said channel region is in the range of approximately 0.1 to 0.5 microns.

Claim 12

The process of claim 8, wherein said gate dielectric layer comprises an oxide selected from the group comprising Be x O y , Mg x O y , ZrO 2 , Ca x O y , TiO 2 , and Ta 2 O 5 .

Claim 13

The process of claim 8, wherein the step of forming said conductive gate layer comprises depositing a polysilicon layer by thermally decomposing silane in a CVD reactor chamber maintained at a temperature in the range of approximately 580 to 650° C. and a pressure of less than approximately 2 torrs and, thereafter, introducing a gate impurity distribution into said polysilicon layer wherein a concentration of said impurity distribution is sufficient to reduce a sheet resistivity of said polysilicon to less than approximately 50 Ω/square.

Claim 14

The process of claim 1, wherein said first implant energy is in the range of approximately 50 to 1000 keV and said first implant dose is in the range of approximately 1×10 13 to 5×10 15 atoms/cm 2 .

Claim 15

The process of claim 1, wherein said second implant energy is in the range of approximately 50 to 1000 keV and said second implant dose is in the range of approximately 1×10 13 to 5×10 15 atoms/cm 2 , and further wherein said second implant energy is greater than said first implant energy.

Claim 16

The process of claim 8, wherein the step of patterning said conductive gate layer comprises forming a patterned photoresist layer on said conductive gate layer and, thereafter, performing a plasma etch process to remove portions of said conductive gate layer not protected by said patterned mask.

Claim 17

The process of claim 8 wherein the step of implanting said source/drain impurity distribution comprises implanting arsenic, phosphorous, or boron into said source/drain regions, and further wherein a peak concentration of said source/drain impurity distribution is in excess of approximately 1×10 19 atoms/cm 3 .