Patent US6341323B2 successfully refreshed from Google Patents.
US6341323B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Information processing system
Assignee: Hitachi Ltd
•
Filing: 2001-02-07
•
Granted: 2002-01-22
•
Expires: 2021-02-07
Abstract
Abstract In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.
Inventors
- 👤 Nobukazu Kondo
- 👤 Seiji Kaneko
- 👤 Koichi Okazawa
- 👤 Hideaki Gemma
- 👤 Tetsuya Mochida
- 👤 Takehisa Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:57
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027; G06F13/14; G06F13/36
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
80 words
An information processing system comprising: a processor; a processor bus which is coupled to said processor, and which operates under a first split bus protocol; a device; a system bus which is coupled to said device, and which operates under a second split bus protocol; and a bus adapter which includes a processor bus interface coupled to said processor bus and a system bus interface coupled to said system bus, and which couples said processor bus with said system bus.
Claim 2
Dependent Claim
80 words
An information processing system comprising: a processor; a processor bus which is coupled to said processor, and which operates under a first split bus protocol; a device; a system bus which is coupled to said device, and which operates under a second split bus protocol; and a bus adapter which includes a processor bus interface coupled to said processor bus and a system bus interface coupled to said system bus, and which couples said processor bus with said system bus.
Claim 3
Dependent Claim
18 words
An information processing system according to claim 1 , wherein said system bus is an address/data multiplexed type.
Claim 4
Dependent Claim
118 words
An information processing system comprising: a processor; a processor bus which is coupled to said processor, and which operates under a first split bus protocol; a device; a system bus which is coupled to said device, and which operates under a second split bus protocol; and a bus adapter which includes a processor bus interface coupled to said processor bus and a system bus interface coupled to said system bus, and which couples said processor bus with said system bus; wherein said processor obtains a processor bus mastership for outputting a read request to said device, and wherein said device obtains a system bus mastership for outputting data in response to said read request outputted by said processor.
Claim 5
Dependent Claim
118 words
An information processing system comprising: a processor; a processor bus which is coupled to said processor, and which operates under a first split bus protocol; a device; a system bus which is coupled to said device, and which operates under a second split bus protocol; and a bus adapter which includes a processor bus interface coupled to said processor bus and a system bus interface coupled to said system bus, and which couples said processor bus with said system bus; wherein said processor obtains a processor bus mastership for outputting a read request to said device, and wherein said device obtains a system bus mastership for outputting data in response to said read request outputted by said processor.
Claim 6
Dependent Claim
18 words
An information processing system according to claim 3 , wherein said system bus is an address/data multiplexed type.
Claim 7
Dependent Claim
67 words
An information processing system comprising: a processor; a processor bus which is coupled to said processor, and which operates under a first split bus protocol; a device; a system bus which is coupled to said device, and which operates under a second split bus protocol; and a bus adapter which couples said processor bus with said system bus; wherein said system bus is an address/data multiplexed type.
Claim 8
Dependent Claim
67 words
An information processing system comprising: a processor; a processor bus which is coupled to said processor, and which operates under a first split bus protocol; a device; a system bus which is coupled to said device, and which operates under a second split bus protocol; and a bus adapter which couples said processor bus with said system bus; wherein said system bus is an address/data multiplexed type.
Claim 9
Dependent Claim
77 words
An information processing system comprising: a processor; a processor bus which is coupled to said processor; a device; a system bus which is coupled to said device; and a bus adapter which couples said processor bus with said system bus; wherein said information processing system executes a data transfer between said processor and said device using said processor bus and said system bus which employ a first split bus protocol and a second split bus protocol, respectively.
Claim 10
Dependent Claim
77 words
An information processing system comprising: a processor; a processor bus which is coupled to said processor; a device; a system bus which is coupled to said device; and a bus adapter which couples said processor bus with said system bus; wherein said information processing system executes a data transfer between said processor and said device using said processor bus and said system bus which employ a first split bus protocol and a second split bus protocol, respectively.
Claim 11
Dependent Claim
18 words
An information processing system according to claim 6 , wherein said system bus is an address/data multiplexed type.
Claim 12
Dependent Claim
90 words
An information processing system comprising: a processor; a processor bus which is coupled to said processor, and which employs a first split bus protocol; a device; a system bus which is coupled to said device, and which employs a second split bus protocol; and a bus adapter which couples said processor bus with said system bus; wherein said processor obtains a processor bus mastership for sending a read request to said device, and wherein said device obtains a system bus mastership for responding said read request issued by said processor.
Claim 13
Dependent Claim
90 words
An information processing system comprising: a processor; a processor bus which is coupled to said processor, and which employs a first split bus protocol; a device; a system bus which is coupled to said device, and which employs a second split bus protocol; and a bus adapter which couples said processor bus with said system bus; wherein said processor obtains a processor bus mastership for sending a read request to said device, and wherein said device obtains a system bus mastership for responding said read request issued by said processor.
Claim 14
Dependent Claim
18 words
An information processing system according to claim 8 , wherein said system bus is an address/data multiplexed type.
Claim 15
Dependent Claim
103 words
An information processing system comprising: a processor; a processor bus which is coupled to said processor, and which operates under a first split bus protocol; a device; a system bus which is coupled to said device, and which operates under a second split bus protocol; and a bus adapter which couples said processor bus with said system bus; wherein said device is an external device of said bus adapter, wherein said processor obtains a processor bus mastership for sending a read request to said device, and wherein said device obtains a system bus mastership for responding said read request issued by said processor.
Claim 16
Dependent Claim
103 words
An information processing system comprising: a processor; a processor bus which is coupled to said processor, and which operates under a first split bus protocol; a device; a system bus which is coupled to said device, and which operates under a second split bus protocol; and a bus adapter which couples said processor bus with said system bus; wherein said device is an external device of said bus adapter, wherein said processor obtains a processor bus mastership for sending a read request to said device, and wherein said device obtains a system bus mastership for responding said read request issued by said processor.
Claim 17
Dependent Claim
18 words
An information processing system according to claim 10 , wherein said system bus is an address/data multiplexed type.
Claim 18
Dependent Claim
98 words
An information processing system comprising: a first module; a first bus which is coupled to said first module, and which operates under a first split bus protocol; a second module; a second bus which is coupled to said second module, and which operates under a second split bus protocol; and a bus adapter which couples said first bus with said second bus; wherein said first module obtains a first bus mastership for outputting an access request to data in said second module, and wherein said second module obtains a second bus mastership for responding to said access request.
Claim 19
Dependent Claim
98 words
An information processing system comprising: a first module; a first bus which is coupled to said first module, and which operates under a first split bus protocol; a second module; a second bus which is coupled to said second module, and which operates under a second split bus protocol; and a bus adapter which couples said first bus with said second bus; wherein said first module obtains a first bus mastership for outputting an access request to data in said second module, and wherein said second module obtains a second bus mastership for responding to said access request.
Claim 20
Dependent Claim
18 words
An information processing system according to claim 12 , wherein said second bus is an address/data multiplexed type.
References Cited (Backward Citations)
US3997896A
Cited
US4128883A
Cited
US4290102A
Cited
US4232366A
Cited
US4281380A
Cited
US4543628A
Cited
US4821174A
Cited
US4941088A
Cited
US4797815A
Cited
US4785394A
Cited
US4953072A
Cited
US5146597A
Cited
US5001625A
Cited
US5235684A
Cited
US5274787A
Cited
US5483642A
Cited
US5237567A
Cited
US5191649A
Cited
US5414820A
Cited
US5341495A
Cited
US5594880A
Cited
US5388224A
Cited
US5379384A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-01-21 | 2005-07-23 | 2006-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-01-21 | 2009-07-23 | 2010-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-01-21 | 2013-07-23 | 2014-01-22 | $7700.00 | Window Closed / Lapsed |