Signal processing system including a bus control module

Claim 2

A signal processing system including a ring bus; a multiplicity of system modules coupled to said ring bus and operative to receive and transfer blocks of data words over said ring bus; and a bus control module coupled to said ring bus and operative to support simultaneous data transfers between specified pairs of system modules which are available adjacent modules along the ring bus or available modules separated by non-involved modules in accordance with concurrent execution of multiple programs of data transfer instructions, said bus control module comprising: first memory means for storing a plurality of programs, each program including a sequence of data transfer instructions, each instruction specifying the pair of system modules corresponding to the instructed data transfer thereof; second memory means for storing a predetermined number of data transfer instructions of each program of said first memory means, each stored instruction of said second memory preassigned an execution priority; first control means operative to execute the data transfer instructions of said second memory means based on a number of factors including the execution priority of the instruction, a transfer readiness of the pair of system modules specified by the instruction, and a bus activity between said specified module pair; and second control means operative to replace data transfer instructions of said second memory means upon the execution thereof with data transfer instructions of said first memory means fetched from corresponding programs in accordance with the sequence of data transfer instructions thereof.

Claim 3

The bus control module in accordance with claim 1 including a bus interfacing means for coupling the bus control module to the ring bus and operative to convert an executable instruction to address and command information specified thereby and to transfer said converted information over the ring bus to the corresponding pair of system modules to initiate data transfer therebetween; and a bus activity monitor for storing instructions during the execution thereof to render the status of the current activity over the ring bus; and wherein the first control means includes means for transferring each executable instruction from the second memory to both said bus interfacing and said bus activity monitor.

Claim 4

The signal processing system in accordance with claim 2 wherein each system module includes means for generating signals representative of its source and destination conditions with regard to data transfer readiness; wherein the first control means includes logic means and means for accessing resident instructions from the second memory means to said logic means for evaluation therein, said logic means operative to determine an executable instruction from said accessed instructions based on the execution priority codes thereof, the source and destination condition signals from the system modules specified thereby, and the current bus activity status as rendered by the bus activity monitor; and wherein the first control means including means for transferring said determined executable instruction from said logic means to the bus interfacing means for execution thereof.

Claim 5

The bus control module in accordance with claim 1 wherein the second control means includes means for detecting that an instruction of the second memory has been executed; means for determining the program of the executed instruction; and means for accessing the next instruction in sequence of said determined program from the first memory to replace the detected executed instruction of the second memory.

Claim 6

The signal processing system in accordance with claim 1 wherein the ring bus comprises individual bus segments for system module to system module coupling about said ring.

Claim 7

A signal processing system including a plurality of ring buses; a multiplicity of system modules coupled to each of said ring buses and operative to receive and transfer blocks of data words over said ring buses; and bus control module coupled to each of said ring buses and operative to support simultaneous data transfers between specified pairs of system modules in accordance with concurrent execution of multiple programs of data transfer instructions, said bus control module comprising: first memory means for storing a plurality of programs, each program including a sequence of data transfer instructions, each instruction specifying the pair of system modules corresponding to the instructed data transfer thereof; second memory means for storing a predetermined number of data transfer instructions of each program of said first memory means, each stored instruction of said second memory preassigned an execution priority; first control means operative to execute the data transfer instructions of said second memory means based on a number of factors including the execution priority of the instruction, a transfer readiness of the pair of system modules specified by the instruction, and a bus activity between said specified module pair; and second control means operative to replace data transfer instructions of said second memory means upon the execution thereof with data transfer instructions of said first memory means fetched from corresponding programs in accordance with the sequence of data transfer instructions thereof; a bus interfacing means for each ring bus of said plurality for coupling the bus control module to each ring bus, each bus interfacing means operative to convert an executable instruction to address and command information specified thereby and to transfer said converted information over its associated ring bus to the corresponding pair of system modules to initiate data transfer therebetween over the associated ring bus; and a bus activity monitor for each ring bus for storing instructions during the execution thereof to render the status of the bus activity over its associated ring bus; and wherein the first control means includes means for transferring an executable instruction to the pair of bus interfacing means and bus activity monitor corresponding to a selected ring bus over which the instructed transfer has been determined to occur.

Claim 8

A signal processing system including a plurality of ring buses; a multiplicity of system modules coupled to each of said ring buses and operative to receive and transfer blocks of data words over said ring buses; and bus control module coupled to each of said ring buses and operative to support simultaneous data transfers between specified pairs of system modules in accordance with concurrent execution of multiple programs of data transfer instructions, said bus control module comprising: first memory means for storing a plurality of programs, each program including a sequence of data transfer instructions, each instruction specifying the pair of system modules corresponding to the instructed data transfer thereof; second memory means for storing a predetermined number of data transfer instructions of each program of said first memory means, each stored instruction of said second memory preassigned an execution priority; first control means operative to execute the data transfer instructions of said second memory means based on a number of factors including the execution priority of the instruction, a transfer readiness of the pair of system modules specified by the instruction, and a bus activity between said specified module pair; and second control means operative to replace data transfer instructions of said second memory means upon the execution thereof with data transfer instructions of said first memory means fetched from corresponding programs in accordance with the sequence of data transfer instructions thereof; a bus interfacing means for each ring bus of said plurality for coupling the bus control module to each ring bus, each bus interfacing means operative to convert an executable instruction to address and command information specified thereby and to transfer said converted information over its associated ring bus to the corresponding pair of system modules to initiate data transfer therebetween over the associated ring bus; and a bus activity monitor for each ring bus for storing instructions during the execution thereof to render the status of the bus activity over its associated ring bus; and wherein the first control means includes means for transferring an executable instruction to the pair of bus interfacing means and bus activity monitor corresponding to a selected ring bus over which the instructed transfer has been determined to occur.

Claim 9

The signal processing system in accordance with claim 6 wherein each system module includes means for generating signals representative of its source and destination conditions with regard to data transfer readiness; wherein the first control means includes logic means and means for accessing resident instructions from the second memory means to said logic means for evaluation therein, said logic means operative to determine an executable instruction from said accessed instructions based on the execution priority codes thereof, the source and destination condition signals from the system modules specified thereby, and the current bus activity status as rendered by the bus activity monitors, and operative to select one of the ring buses for the instructed data transfer of said determined executable instruction based on the current bus activity status as rendered by the bus activity monitors; and wherein the first control means includes means for transferring said determined executable instruction to the pair of bus interfacing means and bus activity monitor corresponding to said selected ring bus.

Claim 10

The bus control module in accordance with claim 7 wherein the first control means includes: means for identifying an instruction which would be executable except for a conflict of its instructed data transfer with the current bus activity of all of the ring buses; means for suspending execution of a selected data transfer based on the priority codes of its corresponding instruction and said identified instruction, and for executing said identified instruction in place of said selected instruction; and means for resuming execution of said selected instruction in accordance with the status of the bus activity as rendered by the bus activity monitor.