Bus system for use with information processing apparatus

Claim 2

An information processing system, comprising: a processor; a processor bus connected to said processor; a main storage; a memory bus connected to said main storage; a connected device; a system bus connected to said connected device; a three-way connection controller for connecting said processor bus, said memory bus and said system bus in an interconnection thereof enabling first operations comprising a first transfer operation between said processor bus and said memory bus and a second transfer operation on said system bus independent of said first transfer operation when said processor bus is connected to said memory bus; and, said three-way connection controller further enabling second operations comprising a third transfer operation between said system bus and said memory bus and a fourth transfer operation on said processor bus independent of said third transfer operation when said system bus is connected to said memory bus; and wherein said processor bus is connected to said system bus through said three-way controller for transfer operation therebetween so that said processor bus, said memory bus and said system bus are connected for operating physically independently of one another.

Claim 3

The information processing system according to claim 1, wherein at least one of said processor bus, said memory bus and said system bus is an address/data multiplexer type.

Claim 4

The information processing system according to claim 1, wherein said three-way connection controller comprises: connection controller means for outputting a dam bus control signal when a one of the transfer operations is made between any two of said processor bus, said memory bus and said system bus; and data switch means responding to said data bus control signal provided from said connection controller means for indicating a connection between at least two data buses from among said processor bus, said memory bus and said system bus.

Claim 5

The information processing system according to claim 3, wherein at least one of said processor bus, said memory bus and said system bus is an address/data multiplexed type.

Claim 6

The information processing system according to claim 3, wherein said data switch means comprises: a plurality of latch means each provided for said processor bus, said memory bus and said system bus for latching data on data buses wherein said data buses comprise a dambus of said process or bus, a data bus of said memory bus and a data bus of said system bus; first generate means for generating a select signal in response to said data bus control signal provided from said connection controller means; and a plurality of first select means each provided for said processor bus, said memory bus and said system bus and responding to said select signal provided from said first generate means for selecting two among three outputs of said latch means corresponding to a selected two of said processor bus, said memory bus and said system bus.

Claim 7

The information processing system according to claims 5, wherein at least one of said processor bus, said memory bus and said system bus is an address/data multiplexed type.

Claim 8

The information processing system according to claim 3, wherein said connection controller means comprises: second select means for selecting either an address signal of said processor bus or an address signal of said system bus to send to an address bus of said memory bus based on information on whether said processor or said connected device transfers data with said main storage; and second generate means signal and a control signal of said processor bus (111 ) and an address signal and to generate at least said data bus control signal, a select signal to said second select means and a control signal to said memory bus based on an address signal and a control signal of said processor bus and an address signal and a control signal of said system bus for determining whether either said processor or said connected device transfers data with said main storage.

Claim 9

The information processing system according to claim 7, wherein at least one of said processor bus, said memory bus and said system bus is an address/data multiplexed type.

Claim 10

An information processing system comprising: a processor; a processor bus connected to said processor; a main storage; a memory bus connected to said main storage; a connected device; a system bus connected to said connected device; a three-way connection controller for connecting, based on control signals and address signals respectively provided from said processor bus and said memory bus, said processor bus, said memory bus and said system bus in an interconnection thereof enabling independent operations between a data transfer operation between a said processor bus and said memory bus and data transfer operation on said system bus when said processor bus is connected to said memory bus based on control signals and address signals respectively provided from said processor bus and said memory bus, and enabling independent operations between a data transfer operation between said system bus and said memory bus and a data transfer operation on said processor bus when said system bus is connected to said memory bus based on control signals and address signals respectively provided from said processor bus and said memory bus; and wherein said processor bus is connected to said system bus through said three-way controller for a data transfer operation therebetween so that said processor bus, said memory bus and said system bus are connected for operating physically independently of one another.

Claim 11

An information processing system comprising: a processor; a processor bus connected to said processor; a main storage; a memory bus connected to said main storage; a connected device; a system bus connected to said connected device; a three-way connection controller for connecting, based on control signals and address signals respectively provided from said processor bus and said memory bus, said processor bus, said memory bus and said system bus in an interconnection thereof enabling independent operations between a data transfer operation between a said processor bus and said memory bus and data transfer operation on said system bus when said processor bus is connected to said memory bus based on control signals and address signals respectively provided from said processor bus and said memory bus, and enabling independent operations between a data transfer operation between said system bus and said memory bus and a data transfer operation on said processor bus when said system bus is connected to said memory bus based on control signals and address signals respectively provided from said processor bus and said memory bus; and wherein said processor bus is connected to said system bus through said three-way controller for a data transfer operation therebetween so that said processor bus, said memory bus and said system bus are connected for operating physically independently of one another.

Claim 12

The information processing system according to claim 9, wherein at least one of said processor bus, said memory bus and said system bus is an address/data multiplexed type.

Claim 13

The information processing system according to claim 9, wherein said three-way connection controller comprises: connection controller means for outputting a data bus control signal when one of the data transfer operations is made between any two of said processor bus, said memory bus and said system bus; and data switch means responding to said data bus control signal provided from said connection controller means for indicating connection between at least two data buses from among said processor bus, said memory bus and said system bus.

Claim 14

The information processing system according to claim 11, wherein at least one of said processor bus, said memory bus and said system bus is an address/data multiplexed type.

Claim 15

The information processing system according to claim 11, wherein said data switch means comprises: a plurality of latch means each provided for said processor bus, said memory bus and said system bus for latching data on data buses wherein said data buses comprise a data bus of said processor bus, a data bus of said memory bus and a data bus of said system bus; first generate means for generating a select signal in response to said data bus control signal provided from said connection controller means; and a plurality of first select means each provided for said processor bus, said memory bus and said system bus and responding to said select signal provided from said first generate means for selecting two among three outputs of said latch means corresponding to a selected two of said processor bus, said memory bus and said system bus.

Claim 16

The information processing system according to claim 13, wherein at least one of said processor bus, said memory bus and said system bus is an address/dam multiplexed type.

Claim 17

The information processing system according to claim 11, wherein said connection controller means comprises: a second select means for selecting either an address signal of said processor bus or an address signal of said system bus to send to an address bus of said memory bus based on information on whether said processor or said connected device transfers data with said main storage; and second generate means to generate at least said data bus control signal, a select signal to said second select means and a control signal to said memory bus based on an address signal and a control signal of said processor bus and an address signal and a control signal of said system bus for determining whether either said processor or said connected device transfers data with said main storage.

Claim 18

The information processing system according to claim 15, wherein at least one of said processor bus, said memory bus and said system bus is an address/data multiplexed type.

Claim 19

An information processing system comprising: a processor; a processor bus connected to said processor; a main storage; a memory bus connected to said main storage; a connected device; a system bus connected to said connected device; and a three-way connection controller for connecting said processor bus, said memory bus and said system bus for enabling independent operations thereamong and including: connection controller means connected to control buses and address buses of said processor bus, said memory bus and said system bus responsive to a control signal and an address signal provided from said processor to said processor bus, a control signal and an address signal provided from said main storage to said memory bus, and a control signal and an address signal provided from said connected device to said system bus for controlling said processor bus, said memory bus and said system bus to output a data bus control signal when said transfer operation is made through a plurality of buses among said processor bus, said memory bus and said system bus; and, data switch means connected to respective data buses of said processor bus, said memory bus and said system bus and responding to said data bus control signal provided from said connection controller means for indicating connection between two data buses from among said processor bus, said memory bus and said system bus wherein said dam switch means comprises: a plurality of latch means each provided for said processor bus, said memory bus and said system bus for latching data on said data buses wherein said data buses comprise a data bus of said processor bus, a data bus of said memory bus and a data bus of said system bus; first generate means for generating a select signal in response to said data bus control signal provided from said connection controller means; and a plurality of first select means each provided for said processor bus, said memory bus and said system bus and responding to said select signal provided from said first generate means for selecting two among three outputs of said latch means for said processor bus, said memory bus and said system bus.

Claim 20

An information processing system comprising: a processor; a processor bus connected to said processor; a main storage; a memory bus connected to said main storage; a connected device; a system bus connected to said connected device; and a three-way connection controller for connecting said processor bus, said memory bus and said system bus for enabling independent operations thereamong and including: connection controller means connected to control buses and address buses of said processor bus, said memory bus and said system bus responsive to a control signal and an address signal provided from said processor to said processor bus, a control signal and an address signal provided from said main storage to said memory bus, and a control signal and an address signal provided from said connected device to said system bus for controlling said processor bus, said memory bus and said system bus to output a data bus control signal when said transfer operation is made through a plurality of buses among said processor bus, said memory bus and said system bus; and, data switch means connected to respective data buses of said processor bus, said memory bus and said system bus and responding to said data bus control signal provided from said connection controller means for indicating connection between two data buses from among said processor bus, said memory bus and said system bus wherein said dam switch means comprises: a plurality of latch means each provided for said processor bus, said memory bus and said system bus for latching data on said data buses wherein said data buses comprise a data bus of said processor bus, a data bus of said memory bus and a data bus of said system bus; first generate means for generating a select signal in response to said data bus control signal provided from said connection controller means; and a plurality of first select means each provided for said processor bus, said memory bus and said system bus and responding to said select signal provided from said first generate means for selecting two among three outputs of said latch means for said processor bus, said memory bus and said system bus.

Claim 21

The infomation processing system according to claim 17, wherein at least one of said processor bus, said memory bus and said system bus is an address/data multiplexed type.

Claim 22

The information processing system according to claim 17, wherein said connection controller means comprises: second select means for selecting either an address signal of said processor bus or an address signal of said system bus to send to an address bus of said memory bus based on information on whether said processor or said connected device transfers data with said main storage; and second generate means to generate at least said data bus control signal, a select signal to said second select means and a control signal to said memory bus based on an address signal and a control signal of said processor bus and an address signal and a control signal of said system bus for determining whether either said processor or said connected device transfers data with said main storage.

Claim 23

The information processing system according to claim 19, wherein at least one of said processor bus, said memory bus and said system bus is an address/data multiplexed type.