US4016546A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bus switch coupling for series-coupled address bus sections in a microprocessor
Assignee: Motorola Solutions Inc
•
Filing: 1975-09-17
•
Granted: 1977-04-05
•
Expires: 1995-09-17
Abstract
Abstract A microprocessor includes a data bus and an address bus. The address bus has first and second sections coupled together in series by bus switch circuitry. The microprocessor also includes control circuitry for controlling various data transfers in the microprocessor. The bus switch circuitry includes a plurality of MOSFETs each having their gate electrodes coupled to the control circuitry and having their sources and drains coupled to corresponding bus conductors of the first and second sections of the address bus. A program counter, incrementer and other working registers are coupled between the address bus first section and the data bus. An accumulator register and an arithmetic logic unit are coupled between the second section of address bus and the data bus.
Inventors
- 👤 Thomas H. Bennett
- 👤 Earl F. Carlow
- 👤 Anthony E. Kouvoussis
- 👤 Rodney H. Orgill
- 👤 Charles Peddle
- 👤 Michael F. Wiles
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 16:38
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/342; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7832; G06F9/30003; G06F9/30076; G06F9/30079; G06F9/32; G06F9/355; G06F9/3557
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
199 words
A microprocessor unit comprising: a data bus; an address bus; a plurality of registers coupled between said data bus and said address bus for storing digital information to effect operation of said microprocessor unit; an arithmetic logic circuit coupled between said address bus and said data bus for performing computations on digital information to effect operation of said microprocessor unit; control means coupled to said arithmetic logic unit and said registers for controlling transfers of data at said arithmetic logic unit and at said registers; said address bus including first and second sections each containing a plurality of bus conductors; a plurality of field effect transistors, each having a first electrode, a second electrode, and a gate electrode; each of said field effect transistors having its first electrode coupled to a respective one of said bus conductors of said first section and having its second electrode coupled to a corresponding one of said bus conductors of said second section; said control means being coupled to the gate electrodes of each of said field effect transistors for electrically coupling said bus conductors of said first section to said bus conductors of said second section under control of said control means.
Claim 2
Dependent Claim
199 words
A microprocessor unit comprising: a data bus; an address bus; a plurality of registers coupled between said data bus and said address bus for storing digital information to effect operation of said microprocessor unit; an arithmetic logic circuit coupled between said address bus and said data bus for performing computations on digital information to effect operation of said microprocessor unit; control means coupled to said arithmetic logic unit and said registers for controlling transfers of data at said arithmetic logic unit and at said registers; said address bus including first and second sections each containing a plurality of bus conductors; a plurality of field effect transistors, each having a first electrode, a second electrode, and a gate electrode; each of said field effect transistors having its first electrode coupled to a respective one of said bus conductors of said first section and having its second electrode coupled to a corresponding one of said bus conductors of said second section; said control means being coupled to the gate electrodes of each of said field effect transistors for electrically coupling said bus conductors of said first section to said bus conductors of said second section under control of said control means.
Claim 3
Dependent Claim
67 words
In a microprocessor unit including a first register for storing digital information, a second register for storing digital information, and control means coupled to said first and second registers for controlling data transfers in said microprocessor unit, bus control and coupling circuitry comprising: a first group of bus conductors each coupled to said first register; a second group of bus conductors each coupled to said second register;
Claim 4
Dependent Claim
67 words
In a microprocessor unit including a first register for storing digital information, a second register for storing digital information, and control means coupled to said first and second registers for controlling data transfers in said microprocessor unit, bus control and coupling circuitry comprising: a first group of bus conductors each coupled to said first register; a second group of bus conductors each coupled to said second register;
Claim 5
Dependent Claim
89 words
a plurality of field-effect transistors each having a first electrode, a second electrode and a gate electrode; each of said field-effect transistors having its first electrode coupled to a responsive one of said bus conductors of said first group and having its second electrode coupled to a respective one of said bus conductors of said second group; each of said field-effect transistors having its gate electrode coupled to said control means in order to effect electrical coupling between said bus conductors coupled to said respective first and second electrodes.
Claim 6
Dependent Claim
89 words
a plurality of field-effect transistors each having a first electrode, a second electrode and a gate electrode; each of said field-effect transistors having its first electrode coupled to a responsive one of said bus conductors of said first group and having its second electrode coupled to a respective one of said bus conductors of said second group; each of said field-effect transistors having its gate electrode coupled to said control means in order to effect electrical coupling between said bus conductors coupled to said respective first and second electrodes.
Claim 7
Dependent Claim
52 words
The bus control and coupling circuitry as recited in claim 2 further including preconditioning means coupled to each of said bus conductors of said second group and to said control means for presetting each of said bus conductors of said second group to a predetermined level under control of said control means.
Claim 8
Dependent Claim
80 words
The bus control and coupling circuitry as recited in claim 2 wherein preconditioning circuit means includes a voltage conductor and a second plurality of field-effect transistors each having a first electrode, a second electrode, and a control electrode, each of said second plurality of field-effect transistors having its first electrode coupled to said voltage conductor, its gate electrode coupled to said control means, and its second electrode coupled to a respective one of said bus conductors of said second group.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-04-04 | 1980-10-04 | 1981-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-04-04 | 1984-10-04 | 1985-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-04-04 | 1988-10-04 | 1989-04-05 | $7700.00 | Window Closed / Lapsed |