EP0141302A2
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EP
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Data processing system
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1984-10-09
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Granted: —
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Expires: 2004-10-09
Abstract
Abstract Data processing system architecture in which a central processing unit CPU (1) and a plurality of input/output processors I/OP (5-1, ... 5-N) said I/OP being connected in parallel through a BUS (6) can have access to a common working memory (4), under control of a memory access control unit (2), through a set of tridirectional gates (3) directly connecting memory (4) to the CPU (1) or to BUS (6) without interposition of registers, drivers, receivers, except said tridirectional gates, between internal CPU channel and memory channel. Control unit (2) periodically monitors, in synchronism with internal CPU cycles if memory access requests from the I/OP are pending and, missing such requests, CPU may activate memory cycles in synchronism with its internal cycles without preamble dialogue and access waiting time. If I/OP memory access requests are pending, control unit grants access to one I/OP on priority basis, activates a memory cycle and monitors in time relation with the memory cycle if other I/OP memory access requests are pending, further granting memory access without delay at the end of the memory cycle. Missing further I/O memory access requests, control unit (2) resynchronizes its memory access request monitoring with the CPU internal cycles.
Inventors
- 👤 Franco Ciacci
- 👤 Vincenzo Pizzoferrato
- 👤 Giancarlo Tessera
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 13:03
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/18
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
322 words
Data processing system architecture where a central processor (CPU) (1) and a plurality of input/output processors (I/OP) (5-1, ..., 5-N) communicate with a common memory (4) and operate in a way asynchronous and independent the one frcm the other on the basis of internal cycles, and a memory access control unit (2) in said CPU receives memory access requests from said CPU and said I/OP and grants access to only one I/OP at a time or to said CPU solving access conflicts on the basis of a preesta blished priority assigned to said access requests, charcterized by that it comprises: - a system bus (6) for the parallel connection of said I/OP - a memory access control unit in said CPU comprising a set of gates (3) - for the selective connection of an input/output internal channel (7A) of said CPU with an input/output channel (8A) of said memory and of said system bus with said memory input/output channel - control means in said control unit for periodically monitoring in syn chronism with the CPU internal cycles, the presence of access requests from said I/OP, for controlling, when I/OP access requests are not pre sent, said set of gates to connect said CPU internal channel to said memory channel and for transferring a possible memory activation can- mand generated by said CPU to said memory, - timing means (43, 56) in said control unit, activated by the detection of said I/OP access requests, for generating a timing cycle of said control means, said control means during said timing cycle provi ding for the generation of signal allowing bus access to the most priority I/OP among the ones concurrently requesting access, for the control of said set of gates to connect said bus with said memory input/output channel, for the generation of a memory activation command, for the acknowledging, in timed relation with said timing cycle, the presence of further I/OP access requests.
Claim 2
Dependent Claim
322 words
Data processing system architecture where a central processor (CPU) (1) and a plurality of input/output processors (I/OP) (5-1, ..., 5-N) communicate with a common memory (4) and operate in a way asynchronous and independent the one frcm the other on the basis of internal cycles, and a memory access control unit (2) in said CPU receives memory access requests from said CPU and said I/OP and grants access to only one I/OP at a time or to said CPU solving access conflicts on the basis of a preesta blished priority assigned to said access requests, charcterized by that it comprises: - a system bus (6) for the parallel connection of said I/OP - a memory access control unit in said CPU comprising a set of gates (3) - for the selective connection of an input/output internal channel (7A) of said CPU with an input/output channel (8A) of said memory and of said system bus with said memory input/output channel - control means in said control unit for periodically monitoring in syn chronism with the CPU internal cycles, the presence of access requests from said I/OP, for controlling, when I/OP access requests are not pre sent, said set of gates to connect said CPU internal channel to said memory channel and for transferring a possible memory activation can- mand generated by said CPU to said memory, - timing means (43, 56) in said control unit, activated by the detection of said I/OP access requests, for generating a timing cycle of said control means, said control means during said timing cycle provi ding for the generation of signal allowing bus access to the most priority I/OP among the ones concurrently requesting access, for the control of said set of gates to connect said bus with said memory input/output channel, for the generation of a memory activation command, for the acknowledging, in timed relation with said timing cycle, the presence of further I/OP access requests.
Claim 3
Dependent Claim
23 words
System architecture as per claim 1 characterized by that said set of ga tes (3) consists of a set of tridirectional transmitting/receiving gates
Claim 4
Dependent Claim
39 words
System architecture as per claim 2, characterized by that said set of gates (3) selectively connects, on command from said control unit, said CPU internal channel (7A) to both said input/output memory channel (8A) and to said bus (6).
Claim 5
Dependent Claim
154 words
System architecture as per claim 3 characterized by that said CPU compri ses means (16) for generating an input/output command and that each I/OP comprises means (95) able to receive such I/OP command, a comparator (101) having the input connected to said bus to compare a binary code, generated by said CPU and transferred through said set of gates on both said input/output memory channel and on said bus with an internal recognition code, and by that one at least of said I/OP comprises an inter face register (69, 70) having the input connected to said bus, for the loading in said interface register, at the reception of said input/aut put command by said I/OP and when said binary code coincides with said internal recognition code, said binary code together with other informa tion generated by said CPU and transferred through said set of gates on both said input/output memory channel and said bus.
References Cited (Backward Citations)
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