Data processing system architecture

Claim 1

A data processing system architecture where a central processor unit (CPU) and a plurality of input/output processors (I/OP) communicate with a common memory and operate in an asynchronous manner and independent the one from the other on the basis of internal cycles, and a memory access control unit in said CPU receives memory access requests from said CPU and said I/OP and grants access to only one I/OP at a time or to said CPU resolving access conflicts on the basis of pre-established priority assigned to said access requests, said data processing system architecture comprising: (a) a system bus for the parallel connection of said I/OP; (b) said memory access control unit in said CPU comprising a set of gates for the selective connection of an input/output internal channel of said CPU with an input/output channel of said memory and the selective connection of said system bus with said input/output channel of said memory; (c) control means in said memory access control unit for periodically monitoring in synchronism with the CPU internal cycles, the presence of access requests from said I/OP, for controlling, when I/OP access requests are not present, said set of gates to connect said input/output internal channel of said CPU to said input/output channel of said memory and for transferring a possible memory activation command generated by said CPU to said memory; and (d) timing means in said memory access control unit and connected to said control means, non-responsive to memory access requests generated by said CPU, activated only by the detection of said I/OP access requests, for generating a timing cycle of said memory access control unit, said memory access control unit during said timing cycle providing for the generation of signal allowing bus access to the highest priority I/OP among the ones concurrently requesting access, for the control of said set of gates to connect, said bus with said input/output channel of said memory, for the generation of a memory activation command, for the acknowledging in a time interval within said timing cycle, the presence of further I/OP access requests, for inhibiting before said time interval, said control means from said periodical monitoring, for enabling said memory access control unit, after said time interval, if further I/OP access requests are detected in said time interval, for the generation of signal allowing bus access to the highest priority I/OP requsting access which has not received the bus access signal, and for enabling said control means to said periodical monitoring, after said time interval, if no further I/OP access request is detected in said time interval.