Patent US6329239B2 successfully refreshed from Google Patents.
US6329239B2
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US
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Dram cell formed on an insulating layer having a vertical channel and a manufacturing method thereof
Assignee: SK Hynix Inc
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Filing: 1999-01-15
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Granted: 2001-12-11
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Expires: 2019-01-15
Abstract
Abstract A semiconductor memory device has a plurality of memory cells arranged in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel. The each memory cell includes a first junction region surrounded by the field oxide layer; a vertical channel including side surfaces, an upper portion and a lower portion, the lower portion of the vertical channel coupled to the first junction region; a second junction region coupled to the upper potion of the vertical channel; a gate electrode surrounding the side surfaces of the vertical channel and including a gate insulator located between the gate electrode and the side surfaces of the vertical channel; a charge storage electrode containing side surfaces, an upper portion and lower portion, the upper potion of the charge storage electrode coupled to the first junction region; a dielectric layer formed on the lower porion and the side surfaces of the charge storage electrode; and a plate electrode entirely surrounding the dielectric layer.
Inventors
- 👤 Yo Hwan Koh
- 👤 Jin Hyeok Choi
- 👤 Sang Won Kang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:59
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/33; H10B12/01; H10B12/02; H10B12/05; H10B12/053; H10D; H10D84/00; H10D84/01; H10D84/0123; H10B12/34; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
215 words
A semiconductor memory device having a plurality of memory cells arranged in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel layer, said each memory cell comprising: a first junction region surrounded by the field oxide layer; a vertical channel layer including side surfaces, a top surface and a bottom surface, the bottom surface of the vertical channel layer formed on the first junction region; a second junction region formed on the top surface of the vertical channel layer; a gate electrode formed on the field oxide layer and surrounding the side surfaces of the vertical channel layer and including a gate insulator located between the gate electrode and the side surface of the vertical channel layer; a charge storage electrode including side surface, a top surface and a bottom surface, the top surface of the charge storage electrode formed under the first junction region; a dielectric layer surrounding the side and bottom surfaces of the charge storage electrode; a plate electrode entirely surrounding the dielectric layer; a bit line contacted to the second junction region, wherein the bit line is overlapped with the charge storage electrode; an insulator layer formed under the plate electrode; and a supporting substrate formed under the isolation layer.
Claim 2
Dependent Claim
215 words
A semiconductor memory device having a plurality of memory cells arranged in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel layer, said each memory cell comprising: a first junction region surrounded by the field oxide layer; a vertical channel layer including side surfaces, a top surface and a bottom surface, the bottom surface of the vertical channel layer formed on the first junction region; a second junction region formed on the top surface of the vertical channel layer; a gate electrode formed on the field oxide layer and surrounding the side surfaces of the vertical channel layer and including a gate insulator located between the gate electrode and the side surface of the vertical channel layer; a charge storage electrode including side surface, a top surface and a bottom surface, the top surface of the charge storage electrode formed under the first junction region; a dielectric layer surrounding the side and bottom surfaces of the charge storage electrode; a plate electrode entirely surrounding the dielectric layer; a bit line contacted to the second junction region, wherein the bit line is overlapped with the charge storage electrode; an insulator layer formed under the plate electrode; and a supporting substrate formed under the isolation layer.
Claim 3
Dependent Claim
28 words
The semiconductor memory device as recited in claim 1 , wherein the first and the second junction region are a source and a drain of the transistor, respectively.
Claim 4
Dependent Claim
35 words
The semiconductor memory device as recited on claim 2 , further comprising a plurality of word lines, each word line coupled to the gate electrode for each of the memory cell arranged on a line.
Claim 5
Dependent Claim
22 words
The semiconductor memory device as recited in claim 1 , further comprising a horizontal channel type MOS transistor for a peripheral circuitry.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-12-10 | 2005-06-11 | 2005-12-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-12-10 | 2009-06-11 | 2009-12-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-12-10 | 2013-06-11 | 2013-12-11 | $7700.00 | Window Closed / Lapsed |