US6311313B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
X-Y grid tree clock distribution network with tunable tree and grid networks
Assignee: International Business Machines Corp
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Filing: 1998-12-29
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Granted: 2001-10-30
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Expires: 2018-12-29
Abstract
Abstract An X-Y grid tree clock distribution network for distributing a clock signal across a VLSI chip. Tunable wiring tree networks are combined with an X-Y grid vertically and horizontally connecting all the tree end points. No drivers are necessary at connection points of the tree end points to the X-Y grid. The final X-Y grid distributes the clock signal close to every place it is needed, and reduces skew across local regions. A tuning method allows buffering of the clock signal, while minimizing both nominal clock skew and clock uncertainty. The tuned tree networks provide low skew even with variations in clock load density and non-ideal buffer placement, while minimizing the number of buffers needed. The tuning method first represents a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load. Next, a smoothing of the clustered grid loads approximates the effect of the X-Y grid. Electrical simulation models are created for network components and clustered grid loads are substituted with smoothed clustered grid loads. A set of N SECTOR electrical net lists are next created by extracting a net list with associated X-Y grid wires cut to isolate each sector net list from its neighboring sectors. Each N SECTOR electrical net list is then tuned, wherein the smoothed clustered grid loads represent an approximation of the effects of the neighboring sectors of each N SECTOR electrical net list.
Inventors
- 👤 Peter J. Camporese
- 👤 Alina Deutsch
- 👤 Timothy Gerard McNamara
- 👤 Phillip John Restle
- 👤 David Allan Webber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 04:17
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
157 words
A clock distribution network, comprising: one or more primary inputs for accepting one or more primary clock signals; a tree coupled to the one or more primary inputs, the tree deriving separate clock signals from the one or more primary clock signals and including N levels of sub-trees where N is greater than 1, wherein the separate clock signals are produced at tree end points and wherein a number of said tree end points for level N is greater than the number of clock signals for level N−1; one or more repower drivers buffering the separate clock signals between any two levels of trees; an X-Y grid vertically and horizontally connecting all the tree end points; wherein no drivers are used at connection points of the tree end points to the X-Y grid; and local distribution wiring, coupled to the X-Y grid, distributing a clock signal on the X-Y grid to one or more clock pin locations.
Claim 2
Dependent Claim
157 words
A clock distribution network, comprising: one or more primary inputs for accepting one or more primary clock signals; a tree coupled to the one or more primary inputs, the tree deriving separate clock signals from the one or more primary clock signals and including N levels of sub-trees where N is greater than 1, wherein the separate clock signals are produced at tree end points and wherein a number of said tree end points for level N is greater than the number of clock signals for level N−1; one or more repower drivers buffering the separate clock signals between any two levels of trees; an X-Y grid vertically and horizontally connecting all the tree end points; wherein no drivers are used at connection points of the tree end points to the X-Y grid; and local distribution wiring, coupled to the X-Y grid, distributing a clock signal on the X-Y grid to one or more clock pin locations.
Claim 3
Dependent Claim
43 words
The network of claim 1 , further comprising: non-uniform load density tuning means for adjusting one or more of: wire widths; and buffer sizes, to reduce one or more undesirable clock network properties selected from the group consisting of: power; skew; and wiring.
Claim 4
Dependent Claim
105 words
The network of claim 1 , further comprising: grid capacitance matrix means for representing a total capacitance of one or more of clock pin loads and twig wiring that are nearest to a respective X-Y grid intersection point as a clustered grid load; and smoothing means for smoothing clustered grid loads to approximate the effect of the X-Y grid; means for creating electrical simulation models for network components and substituting clsutered grid loads with smoothed clustered grid loads; and means for tuning the clock distribution network as a function of the smoothed clustered grid loads to reduce one or more of power; wiring; and skew.
Claim 5
Dependent Claim
88 words
The network of claim 1 , further comprising: isolated sector net list means for creating a set of N SECTOR electrical net lists by extracting a net list with associated X-Y grid wires cut to isolate each sector net list from its neighboring sectors; and means for tuning each N SECTOR electrical net lists to reduce one or more of power; wiring; and skew; wherein the smoothed clustered grid loads represent an approximation of the effects of the neighboring sectors of said each N SECTOR electrical net list.
Claim 6
Dependent Claim
29 words
The network of claim 1 wherein the tree comprises a network of branching wires laid out in a hierarchical succession of one or more H's to form said levels.
Claim 7
Dependent Claim
19 words
The network of claim 1 wherein the tree comprises a network of branching wires designed to avoid various blockages.
Claim 8
Dependent Claim
27 words
The network of claim 1 , further comprising means for providing low skew even when clock buffer locations, clock pin locations, and pin capacitances change during design.
Claim 9
Dependent Claim
23 words
The network of claim 1 , further comprising a set of buffers to condition the signals between any two levels of branching trees.
Claim 10
Dependent Claim
64 words
The network of claim 1 , further comprising: an array of memory cells blocking the placement of a repower driver; means for moving one or more of drivers and wires to accommodate blockages on transistor levels or wiring levels; wire length matching means for equalizing delays; and wire width tuning means for reducing the skew due to the modifications needed to avoid said blockages.
Claim 11
Dependent Claim
28 words
The network of claim 1 wherein local clock block circuits are used to generate one or more local clock signals from the signals at each clock pin location.
Claim 12
Dependent Claim
28 words
The network of claim 1 , wherein all of the plurality of signals within a level less than N of branching trees are interconnected using an X-Y grid.
Claim 13
Dependent Claim
15 words
The network of claim 1 , wherein the X-Y grid is a modified X-Y grid.
Claim 14
Dependent Claim
45 words
The network of claim 1 , wherein the tree or grid wires are implemented as one or more parallel wires composed of alternating signal wires and power or ground wires for the control of transmission line properties, each individual wire width and space being tunable.
Claim 15
Independent Claim
133 words
A method for designing a low clock skew nework when distributing an internal or external clock signal to segments of a chip, the method comprising the steps of: providing an input to accept the clock signal; providing a network of branching wires from the input, forming trees including at least a first level tree and one or more final level trees for deriving a plurality of separate clock signals from the external clock signal; and vertically and horizontally interconnecting all of the separate clock signals after the one or more final level trees in an X-Y grid adapted to transmit the plurality of separate clock signals from the final level of trees to a grid pattern; wherein no drivers are used at connection points of the final level trees to the X-Y grid.
Claim 16
Independent Claim
133 words
A method for designing a low clock skew nework when distributing an internal or external clock signal to segments of a chip, the method comprising the steps of: providing an input to accept the clock signal; providing a network of branching wires from the input, forming trees including at least a first level tree and one or more final level trees for deriving a plurality of separate clock signals from the external clock signal; and vertically and horizontally interconnecting all of the separate clock signals after the one or more final level trees in an X-Y grid adapted to transmit the plurality of separate clock signals from the final level of trees to a grid pattern; wherein no drivers are used at connection points of the final level trees to the X-Y grid.
Claim 17
Dependent Claim
144 words
The method of claim 14 , for tuning the network to reduce one or more of power, wiring, or skew, further comprising the steps of: representing a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load; smoothing clustered grid loads to approximate the effect of the X-Y grid; creating electrical simulation models for network components and substituting clustered grid loads with smoothed clustered grid loads; creating a set of N SECTOR electrical net lists by extracting a net list with associated X-Y grid wires cut to isolate each sector net list from its neighboring sectors; and tuning each electrical net list to reduce one or more of power; wiring; and skew; wherein the smoothed clustered grid loads represent an approximation of the effects of the neighboring sectors of said each N SECTOR electrical net list.
Claim 18
Dependent Claim
18 words
The method of claim 15 , wherein the clustered grid loads are represented in a grid capacitance matrix.
Claim 19
Dependent Claim
31 words
The method of claim 15 , said smoothing step further comprising the step of smoothing the capacitance matrix using Jacobi's method to simulate a smoothing effect of the X-Y grid wiring.
Claim 20
Dependent Claim
33 words
The method of claim 15 , wherein said representing step further comprises the step of clustering X-Y grid wire capacitances, to further reduce the number of electrical elements in the sector net lists.
Claim 21
Dependent Claim
26 words
The method of claim 15 , said tuning step further comprising the step of tuning one or more tunable network parameters using a nonlinear optimization method.
Claim 22
Dependent Claim
31 words
The method of claim 19 , further comprising the step using a reduced order interconnect modeling technique such as RICE to calculate one or more of delays, transition times, and sensitivities.
Claim 23
Dependent Claim
43 words
The method of claim 15 , further comprising the step of simulating a full net list for final full simulation and checking, the net list including tuned wires and buffers, original unclustered pin loads, local clock distribution wiring, and uncut X-Y grid wires.
Claim 24
Dependent Claim
26 words
The method of claim 21 , further comprising the step of analyzing the final full simulation to provide final skew and waveforms at every clock pin.
Claim 25
Dependent Claim
27 words
The method of claim 14 , further comprising the step of providing a set of buffers to condition the signals between any two levels of branching trees.
Claim 26
Dependent Claim
29 words
The method of claim 14 , further comprising the step of interconnecting all the clock signals within a level less than N of branching trees using an X-Y grid.
Claim 27
Dependent Claim
33 words
The method of claim 14 , further comprising the step of routing local clock distribution wiring using branching or non-branching wires from the X-Y grid to clock pin locations needing the clock signal.
Claim 28
Dependent Claim
26 words
The method of claim 14 , further comprising the step of cutting of the X-Y grid of said each electrical net list to remove circuit loops.
Claim 29
Dependent Claim
226 words
A clock distribution network, comprising: one or more primary inputs for accepting one or more primary clock signals; a tree coupled to the one or more primary inputs, the tree deriving separate clock signals from the one or more primary clock signals and including N levels of sub-trees where N is greater than 1, wherein the separate clock signals are produced at tree end points and wherein a number of said tree end points for level N is greater than the number of clock signals for level N−1; one or more repower drivers buffering the separate clock signals between any two levels of trees; an X-Y grid vertically and horizontally connecting all the tree end points; local distribution wiring, coupled to the X-Y grid, distributing a clock signal on the X-Y grid to one or more clock pin locations; grid capacitance matrix means for representing a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load; and smoothing means for smoothing clustered grid loads to approximate the effect of the X-Y grid; means for creating electrical simulation models for network components and substituting clustered grid loads with smoothed clustered grid loads; and means for tuning the clock distribution network as a function of the smoothed clustered grid loads to reduce one or more of power; wiring; and skew.
Claim 30
Dependent Claim
226 words
A clock distribution network, comprising: one or more primary inputs for accepting one or more primary clock signals; a tree coupled to the one or more primary inputs, the tree deriving separate clock signals from the one or more primary clock signals and including N levels of sub-trees where N is greater than 1, wherein the separate clock signals are produced at tree end points and wherein a number of said tree end points for level N is greater than the number of clock signals for level N−1; one or more repower drivers buffering the separate clock signals between any two levels of trees; an X-Y grid vertically and horizontally connecting all the tree end points; local distribution wiring, coupled to the X-Y grid, distributing a clock signal on the X-Y grid to one or more clock pin locations; grid capacitance matrix means for representing a total capacitance of one or more of clock pin loads and twig wiring as a clustered grid load; and smoothing means for smoothing clustered grid loads to approximate the effect of the X-Y grid; means for creating electrical simulation models for network components and substituting clustered grid loads with smoothed clustered grid loads; and means for tuning the clock distribution network as a function of the smoothed clustered grid loads to reduce one or more of power; wiring; and skew.
Claim 31
Dependent Claim
94 words
The network of claim 27 , further comprising: isolated sector net list means for creating a set of N SECTOR electrical net lists by extracting a net list with associated X-Y grid wires cut to isolate each sector net list from its neighboring sectors; and said means for tuning further comprising means for tuning the N SECTOR electrical net lists to reduce one or more of power; wiring; and skew; wherein the smoothed clustered grid loads represent an approximation of the effects of the neighboring sectors of said each N SECTOR electrical net list.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-10-29 | 2005-04-30 | 2005-10-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-10-29 | 2009-04-30 | 2009-10-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-10-29 | 2013-04-30 | 2013-10-30 | $7700.00 | Window Closed / Lapsed |