US6006025A
Expired / Lapsed
US
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Method of clock routing for semiconductor chips
Assignee: International Business Machines Corp
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Filing: 1997-09-22
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Granted: 1999-12-21
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Expires: 2017-09-22
Abstract
Abstract A method of wire routing includes the steps of providing an array of cells on a semiconductor chip, determining a minimum distance location between a first clock point, an second clock point and a drive point for connecting to a connection point in the array of cells, and defining a wire path through an array of blockages disposed in the array of cells from the minimum distance location to the first clock point and from the minimum distance location to the second clock point to create a path for a wire for connecting the first clock point and the second clock point to a connection point such that skew is minimized between the starting clock point and the second clock point from the connection point when a clock signal is provided to the connection point from the drive point.
Inventors
- 👤 Peter William Cook
- 👤 Phillip John Restle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:23
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G06F30/00; G06F30/30; G06F30/39; G06F30/394; G06F30/396
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
140 words
A method of wire routing comprising the steps of: providing an array of cells on a semiconductor chip; determining a minimum distance location between a first clock point, a second clock point and a drive point for connecting to a connection point in the array of cells; and defining a wire path through an array of blockages disposed in the array of cells from the minimum distance location to the first clock point and from the minimum distance location to the second clock point to create the wire path for a wire for connecting the first clock point and the second clock point to the connection point such that skew is minimized between the first clock point and the second clock point from the connection point when a clock signal is provided at the connection point from the drive point.
Claim 2
Independent Claim
140 words
A method of wire routing comprising the steps of: providing an array of cells on a semiconductor chip; determining a minimum distance location between a first clock point, a second clock point and a drive point for connecting to a connection point in the array of cells; and defining a wire path through an array of blockages disposed in the array of cells from the minimum distance location to the first clock point and from the minimum distance location to the second clock point to create the wire path for a wire for connecting the first clock point and the second clock point to the connection point such that skew is minimized between the first clock point and the second clock point from the connection point when a clock signal is provided at the connection point from the drive point.
Claim 3
Dependent Claim
32 words
The method as recited in claim 1 further comprising the step of adjusting the wire for maximizing balance between load and delay between the first clock point and the second clock point.
Claim 4
Dependent Claim
47 words
The method as recited in claim 1 wherein the first clock point and the second clock point include a plurality of clock points and further comprising the step of reducing the number of clock points on the chip by combining the clock points into equivalent clock points.
Claim 5
Dependent Claim
26 words
The method as recited in claim 1 further comprises the step of calculating the distances, delay and load at each cell within the array of cells.
Claim 6
Dependent Claim
24 words
The method as recited in claim 1 further comprises the step of locating the drive point for biasing the location of the wire path.
Claim 7
Dependent Claim
220 words
The method as recited in claim 1 wherein the step of determining a minimum distance location between a first clock point, a second clock point and a drive point in the array of cells further comprises the steps of: pairing the first clock point and the second clock point based on substantially equivalent delay and physical proximity therebetween; counting a first number of cells from the first clock point to the second clock point and a second number of cells from the second clock point to the first clock point assigning each cell a first number representing the first number of cells from the first clock point and a second number representing the second number of cells from the second clock point; selecting the drive point in the array of cells such that a wire path is biased toward the drive point within the array of cells; counting a third number of cells for each cell representing a third number for each cell for a distance to both the first clock point and the second clock point from the drive point; summing the first number, the second number and the third number for each cell to determine a fourth number for each cell; and identifying a minimum distance location based on the cell having the fourth number of lowest value.
Claim 8
Dependent Claim
168 words
The method as recited in claim 1 wherein the step of defining a wire path through an array of blockages further comprises the steps of: defining and adjusting a wire path to avoid blockages in the array of cells, the wire path distance being minimized between the first clock point and the second clock point and from the connection point to the drive point; determining a delay and a load at each cell in the wire path; moving the connection point on the wire path such that delay and load are substantially equal from the connection point to the first clock point and from the connection point to the second clock point; connecting the first clock point to the second clock point through the connection point with a wire; and electrically connecting the connection point to the drive point such that skew is minimized between the first clock point and the second clock point from the connection point when a clock signal is provided at the drive point.
Claim 9
Independent Claim
182 words
A method of wire routing comprising the steps of: providing an array of cells on a semiconductor chip; determining a minimum distance location between a first clock point, a second clock point and a drive point in the array of cells; defining and adjusting a wire path to avoid blockages in the array of cells, the wire path distance being minimized between the first clock point and the second clock point and from connection point to the drive point; determining a delay and a load at each cell in the wire path; moving the connection point on the wire path such that a delay is substantially equal from the connection point to the first clock point and from the connection point to the second clock point; connecting the first clock point to the second clock point through the connection point with a wire; and electrically connecting the connection point to the drive point such that skew is minimized between the first clock point and the second clock point from the connection point when a clock signal is provided at the drive point.
Claim 10
Independent Claim
182 words
A method of wire routing comprising the steps of: providing an array of cells on a semiconductor chip; determining a minimum distance location between a first clock point, a second clock point and a drive point in the array of cells; defining and adjusting a wire path to avoid blockages in the array of cells, the wire path distance being minimized between the first clock point and the second clock point and from connection point to the drive point; determining a delay and a load at each cell in the wire path; moving the connection point on the wire path such that a delay is substantially equal from the connection point to the first clock point and from the connection point to the second clock point; connecting the first clock point to the second clock point through the connection point with a wire; and electrically connecting the connection point to the drive point such that skew is minimized between the first clock point and the second clock point from the connection point when a clock signal is provided at the drive point.
Claim 11
Dependent Claim
45 words
The method as recited in claim 8 wherein the step of moving the connection point on the wire path such that a delay is substantially equal includes moving the connection point on the wire path such that the delay and a load are substantially equal.
Claim 12
Dependent Claim
32 words
The method as recited in claim 8 further comprising the step of adjusting the wire for maximizing balance between load and delay between the first clock point and the second clock point.
Claim 13
Dependent Claim
47 words
The method as recited in claim 8 wherein the first clock point and the second clock point include a plurality of clock points and further comprising the step of reducing the number of clock points on the chip by combining the clock points into equivalent clock points.
Claim 14
Dependent Claim
24 words
The method as recited in claim 8 further comprises the step of locating the drive point for biasing the location of the wire path.
Claim 15
Independent Claim
334 words
A method of wire routing comprising the steps of: providing an array of cells on a semiconductor chip; pairing a first clock point and a second clock point based on substantially equivalent delay and physical proximity therebetween, counting a first number of cells from the first clock point to the second clock point and a second number of cells from the second clock point to the first clock point assigning each cell a first number representing the first number of cells from the first clock point and a second number representing the second number of cells from the second clock point; selecting a drive point in the array of cells such that a wire path is biased toward the drive point disposed within the array of cells; counting a third number of cells for each cell representing a distance to both the first clock point and the second clock point from the drive point; summing the first number, the second number and the third number for each cell to determine a fourth number for each cell; identifying a minimum distance location based on the cell having the fourth number of lowest value; defining and adjusting a wire path to avoid blockages in the array of cells, the wire path distance being minimized between the first clock point and the second clock point and from connection point to the drive point; determining a delay and a load at each cell in the wire path; moving the connection point on the wire path such that delay and load are substantially equal from the connection point to the first clock point and from the connection point to the second clock point; connecting the first clock point to the second clock point through the connection point with a wire; and electrically connecting the connection point to the drive point such that skew is minimized between the first clock point and the second clock point from the connection point when a clock signal is provided at the drive point.
Claim 16
Independent Claim
334 words
A method of wire routing comprising the steps of: providing an array of cells on a semiconductor chip; pairing a first clock point and a second clock point based on substantially equivalent delay and physical proximity therebetween, counting a first number of cells from the first clock point to the second clock point and a second number of cells from the second clock point to the first clock point assigning each cell a first number representing the first number of cells from the first clock point and a second number representing the second number of cells from the second clock point; selecting a drive point in the array of cells such that a wire path is biased toward the drive point disposed within the array of cells; counting a third number of cells for each cell representing a distance to both the first clock point and the second clock point from the drive point; summing the first number, the second number and the third number for each cell to determine a fourth number for each cell; identifying a minimum distance location based on the cell having the fourth number of lowest value; defining and adjusting a wire path to avoid blockages in the array of cells, the wire path distance being minimized between the first clock point and the second clock point and from connection point to the drive point; determining a delay and a load at each cell in the wire path; moving the connection point on the wire path such that delay and load are substantially equal from the connection point to the first clock point and from the connection point to the second clock point; connecting the first clock point to the second clock point through the connection point with a wire; and electrically connecting the connection point to the drive point such that skew is minimized between the first clock point and the second clock point from the connection point when a clock signal is provided at the drive point.
Claim 17
Dependent Claim
32 words
The method as recited in claim 13 further comprising the step of adjusting the wire for maximizing balance between load and delay between the first clock point and the second clock point.
Claim 18
Dependent Claim
47 words
The method as recited in claim 13 wherein the first clock point and the second clock point include a plurality of clock points and further comprising the step of reducing the number of clock points on the chip by combining the clock points into equivalent clock points.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-12-20 | 2003-06-21 | 2003-12-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-20 | 2007-06-21 | 2007-12-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-12-20 | 2011-06-21 | 2011-12-21 | $7700.00 | Window Closed / Lapsed |