Abstract In a layout system of a logic circuit, a buffer inserted into a critical path is arranged/wired in an arranged region of a circuit block of a primitive layout in such a manner that delay time of the critical path in the primitive layout can be limited to an allowable value. The layout system is comprised of unarranged region information extracting means for extracting a position and a size of an unarranged region from layout data after an arranging/wiring process; virtual node inserting means for inserting a virtual node into a wiring segment located adjacent to the unarranged region, the virtual node constituting a connection point between the wiring segment and the unarranged region; wiring parameter extracting means for extracting a wiring parameter constructed of a wiring resistance and a wiring capacitance of the wiring segment; and path delay time calculating means for calculating delay time of a path based upon the wiring parameter and a delay parameter specific to an element.
Inventors
👤 Yasuaki Kuroda
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-27 07:19
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
91 words
A layout system for adjusting a delay of a critical path in a logic circuit comprising: critical path extracting means for extracting said critical path in a primitive layout data; unoccupied region extracting means for extracting a region unoccupied with a circuit block along said critical path in said primitive layout data; size calculating means for calculating a buffer size for adjusting said delay of said critical path into a range of a allowable delay; and buffer inserting means for inserting a buffer into said region unoccupied with said circuit block.
Claim 2
Dependent Claim
91 words
A layout system for adjusting a delay of a critical path in a logic circuit comprising: critical path extracting means for extracting said critical path in a primitive layout data; unoccupied region extracting means for extracting a region unoccupied with a circuit block along said critical path in said primitive layout data; size calculating means for calculating a buffer size for adjusting said delay of said critical path into a range of a allowable delay; and buffer inserting means for inserting a buffer into said region unoccupied with said circuit block.
Claim 3
Dependent Claim
31 words
The layout system as claimed in claim 1, wherein said unoccupied region extracting means extracts said region having a maximum size among unoccupied regions in which said critical path running through.
Claim 4
Dependent Claim
57 words
The layout system as claimed in claim 1, wherein said buffer inserting means inserts a buffer having said buffer size when said buffer size is smaller than said region extracted by said unoccupied region extracting means and a buffer having a maximum size capable to be arranged in said region extracted by said unoccupied region extracting means.
Claim 5
Dependent Claim
41 words
The layout system as claimed in claim 3 further comprising means for invoking said unoccupied region extracting means, size calculating means and said buffer inserting means until there is not any more unoccupied region in which said critical path running through.