Circuit design support system and circuit producing method

Claim 1

A circuit design support system comprising: logic minimizing means for receiving data indicating a functional specification of a desired circuit and for minimizing logical sequences of the desired circuit; cell assignment means, operatively coupled to said logic minimizing means, for assigning cells to each of minimized logical sequences determined by said logic minimizing means and for generating data on a circuit configuration of the desired circuit; load/timing check means, operatively coupled to said cell assignment means, for receiving the data on the circuit configuration and for simultaneously executing a load check and a timing check, said load check determining whether or not the circuit configuration has a load driving ability within a tolerable load driving ability, said timing check determining whether or not the circuit configuration has a delay time of a signal within a tolerable delay time, said load/timing signal check means comprising means for determining whether or not a signal output terminal in the circuit configuration has an overload and for calculating a delay time of a signal path including said signal output terminal assuming that a tolerable load is connected to said signal output terminal; load adjustment means, operatively coupled to said load/timing check means, for executing a load adjustment of the circuit configuration on the basis of a result of the load check so that the load driving ability of said circuit configuration falls within the tolerable driving ability; and timing adjustment means, operatively coupled to said load/timing check means, for executing a timing adjustment of the circuit configuration on the basis of a result of the timing check so that the delay time of said circuit configuration falls within the tolerable delay time.