Method and apparatus for making integrated circuits by inserting buffers into a netlist to control clock skew

Claim 1

A method for making a digital integrated circuit comprising: developing a set of circuit specifications for a digital integrated circuit including a maximum clock skew, a minimum driveability, and a maximum ramp delay; describing said set of circuit specifications in a hardware description language and inputting said hardware description language into a digital computer system; synthesizing on said digital computer system a netlist from said hardware description language which specifies circuitry of said integrated circuit, said synthesized netlist describing at least one clock net; analyzing and inserting buffers as required into said netlist on said digital computer system to create a modified netlist which describes a circuit that has at most said maximum clock skew, at least said minimum driveability, and at most said maximum ramp delay said analyzing and inserting buffers including creating an initial routing for said clock net, computing partial parameters for said clock net by conducting a bottom up scan and a top down scan of said clock net, finding at least one balance point in said clock net based on said partial parameters, and inserting a driver into said clock net at said balance point; and producing a digital integrated circuit as specified by said modified netlist comprising a semiconductor die including said circuitry of said integrated circuit, said semiconductor die having a plurality of I/O pads, a package enclosing said integrated circuit die, a plurality of leads extending from said package, and a plurality of conductors coupling said plurality of I/O pads of said semiconductor die to said plurality of leads.

Claim 2

A method for making a digital integrated circuit comprising: developing a set of circuit specifications for a digital integrated circuit including a maximum clock skew, a minimum driveability, and a maximum ramp delay; describing said set of circuit specifications in a hardware description language and inputting said hardware description language into a digital computer system; synthesizing on said digital computer system a netlist from said hardware description language which specifies circuitry of said integrated circuit, said synthesized netlist describing at least one clock net; analyzing and inserting buffers as required into said netlist on said digital computer system to create a modified netlist which describes a circuit that has at most said maximum clock skew, at least said minimum driveability, and at most said maximum ramp delay said analyzing and inserting buffers including creating an initial routing for said clock net, computing partial parameters for said clock net by conducting a bottom up scan and a top down scan of said clock net, finding at least one balance point in said clock net based on said partial parameters, and inserting a driver into said clock net at said balance point; and producing a digital integrated circuit as specified by said modified netlist comprising a semiconductor die including said circuitry of said integrated circuit, said semiconductor die having a plurality of I/O pads, a package enclosing said integrated circuit die, a plurality of leads extending from said package, and a plurality of conductors coupling said plurality of I/O pads of said semiconductor die to said plurality of leads.

Claim 10

A method for laying out a digital integrated circuit comprising: analyzing on a digital computer system a previously synthesized netlist created by a synthesizer routine implemented on said digital computer system, said previously synthesized netlist describing at least one clock net; inserting into said previously synthesized netlist a description of at least one buffer such that no clock net described by said netlist has greater than a user-defined maximum clock skew, less than a user-defined minimum driveability, and greater than a user-defined maximum ramp delay, thereby creating a modified netlist; and wherein said analyzing and inserting are performed recursively until no clock net has greater than a user-defined maximum clock skew, less than a user-defined minimum driveability, and greater than a user-defined maximum ramp delay, and said analyzing and inserting include: (a) choosing a clock net; (b) creating on said computer system an initial routing comprising an initial sibling of an initial sibling level for said clock net; (c) computing partial parameters for each sibling; (d) finding a balance point of each sibling; (e) dividing each sibling into a plurality of siblings of a subsequent sibling level if all siblings at a sibling level do not have greater than a user-defined maximum clock skew, less than a user-defined minimum driveability, and greater than a user-defined maximum ramp delay, and repeating (c) through (e) until all siblings of a subsequent sibling level meet said criteria; (f) determining if the level is at said initial level and choosing an additional clock net and repeating steps (b) to (f) if it is; and (g) inserting a driver into said clock net at said balance point of each sibling at said subsequent level, resetting the sibling level to said initial sibling level, and repeating (c) to (f) until all clock nets have been processed.

Claim 11

A method for laying out a digital integrated circuit comprising: analyzing on a digital computer system a previously synthesized netlist created by a synthesizer routine implemented on said digital computer system, said previously synthesized netlist describing at least one clock net; inserting into said previously synthesized netlist a description of at least one buffer such that no clock net described by said netlist has greater than a user-defined maximum clock skew, less than a user-defined minimum driveability, and greater than a user-defined maximum ramp delay, thereby creating a modified netlist; and wherein said analyzing and inserting are performed recursively until no clock net has greater than a user-defined maximum clock skew, less than a user-defined minimum driveability, and greater than a user-defined maximum ramp delay, and said analyzing and inserting include: (a) choosing a clock net; (b) creating on said computer system an initial routing comprising an initial sibling of an initial sibling level for said clock net; (c) computing partial parameters for each sibling; (d) finding a balance point of each sibling; (e) dividing each sibling into a plurality of siblings of a subsequent sibling level if all siblings at a sibling level do not have greater than a user-defined maximum clock skew, less than a user-defined minimum driveability, and greater than a user-defined maximum ramp delay, and repeating (c) through (e) until all siblings of a subsequent sibling level meet said criteria; (f) determining if the level is at said initial level and choosing an additional clock net and repeating steps (b) to (f) if it is; and (g) inserting a driver into said clock net at said balance point of each sibling at said subsequent level, resetting the sibling level to said initial sibling level, and repeating (c) to (f) until all clock nets have been processed.

Claim 17

A system for creating integrated circuit masks comprising: (a) a digital hardware description processor including a central processing unit (CPU), digital storage coupled to said CPU, and a user input device coupled to said CPU, said hardware description processor being operative to; (i) create mask generation data from a hardware description of a set of circuit specifications for a digital integrated circuit received from said user input device, said circuit specifications including a maximum clock skew, a minimum driveability, and a maximum ramp delay, (ii) develop a netlist from said hardware description, said netlist specifying circuitry of said integrated circuit and describing at least one clock net, (iii) insert buffers, as required, into said netlist so as to provide a modified netlist which describes an integrated circuit having at most said maximum clock skew, at least said minimum driveability, and at most said maximum ramp delay, by creating an initial routing for said clock net, computing partial parameters for said clock net by conducting a bottom up scan and a top down scan of said clock net, finding at least one balance point in said clock net based on said partial parameters, inserting a driver into said clock net at said balance point; (iv) develop said mask generation data from said modified netlist and store said mask generation data in said digital storage; and (b) a digital mask generator coupled to said digital storage for making at least one integrated circuit mask from said mask generation data stored in said digital storage.

Claim 18

A system for creating integrated circuit masks comprising: (a) a digital hardware description processor including a central processing unit (CPU), digital storage coupled to said CPU, and a user input device coupled to said CPU, said hardware description processor being operative to; (i) create mask generation data from a hardware description of a set of circuit specifications for a digital integrated circuit received from said user input device, said circuit specifications including a maximum clock skew, a minimum driveability, and a maximum ramp delay, (ii) develop a netlist from said hardware description, said netlist specifying circuitry of said integrated circuit and describing at least one clock net, (iii) insert buffers, as required, into said netlist so as to provide a modified netlist which describes an integrated circuit having at most said maximum clock skew, at least said minimum driveability, and at most said maximum ramp delay, by creating an initial routing for said clock net, computing partial parameters for said clock net by conducting a bottom up scan and a top down scan of said clock net, finding at least one balance point in said clock net based on said partial parameters, inserting a driver into said clock net at said balance point; (iv) develop said mask generation data from said modified netlist and store said mask generation data in said digital storage; and (b) a digital mask generator coupled to said digital storage for making at least one integrated circuit mask from said mask generation data stored in said digital storage.