US5557779A
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US
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Method for distributing a clock signal within a semiconductor integrated circuit by minimizing clock skew
Assignee: Toshiba Corp
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Filing: 1995-04-05
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Granted: 1996-09-17
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Expires: 2015-04-05
Abstract
Abstract A control-signal distributing method used in a wiring-pattern network such that a control signal is supplied from root driver cells via repeating buffer cells to terminal cells. The method comprises the steps of: grouping the terminal cells into clusters containing at least one of the terminal cells, forming a binary-tree-shaped wiring pattern path where the root driver cells are root nodes and the clusters are leaf nodes, inserting the repeating buffer cells into the wiring pattern path at which delay time required for control signal transmission in the binary-tree-shaped path is minimized, calculating first delay amounts in a signal path defined from a branch node at a low level of the binary-tree-shaped path to the leaf nodes, setting physical positions of the branch nodes such that a difference among the calculated first delay amounts is minimized, separating the overlapped terminal cells from each other on the binary-tree-shaped path by updating previous information about a circuit connection when the repeating buffer cells are inserted and by correcting arrangement information about terminal cell positions adjacent to the buffer cells, determining a final wiring-pattern path within each of the clusters based upon the corrected arrangement information, calculating second delay amounts in the clusters based on the finally determined wiring-pattern path, determining respective branch node positions based on the second delay amounts, and determining a final wiring-pattern path among the branch nodes.
Inventors
- 👤 Fumihiro Minami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:59
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/10; G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G06F30/00; G06F30/30; G06F30/39; G06F30/394; G06F30/396
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
262 words
A method for distributing a control signal in a wiring-pattern network formed on a semiconductor substrate where said control signal is supplied from a root driver cell via repeating buffer cells to a plurality of terminal cells, the method comprising the steps of: grouping said plurality of terminal cells into a plurality of clusters containing at least one of said terminal cells; forming a binary-tree-shaped wiring pattern path where said root driver cell is constituted as a root node and said clusters are constituted as leaf nodes; inserting said repeating buffer cells as branch nodes into portions of the binary-tree-shaped wiring pattern path at which each of delay times of said control signal propagating therein is minimized and dividing the binary-tree-shaped wiring pattern path into multi-stage hierarchical sub-trees; calculating delay times of said control signal propagating from each of said branch nodes to each of said leaf nodes, said calculating step being successively repeated from the lowermost ones of said branch nodes to the uppermost one of said branch nodes; setting physical positions of said branch nodes on the semiconductor substrate where a difference among said delay times becomes minimum; updating previous entire information about a circuit connection when said repeating buffer cells are inserted; separating said repeating buffer cells from other cells being overlapped with said repeating buffer cells on said binary-tree-shaped wiring pattern path; correcting arrangement information about positions of all the cells on the semiconductor substrate so as not to have any of the cells being overlapped; and determining a final wiring-pattern path among each of said branch nodes.
Claim 2
Independent Claim
262 words
A method for distributing a control signal in a wiring-pattern network formed on a semiconductor substrate where said control signal is supplied from a root driver cell via repeating buffer cells to a plurality of terminal cells, the method comprising the steps of: grouping said plurality of terminal cells into a plurality of clusters containing at least one of said terminal cells; forming a binary-tree-shaped wiring pattern path where said root driver cell is constituted as a root node and said clusters are constituted as leaf nodes; inserting said repeating buffer cells as branch nodes into portions of the binary-tree-shaped wiring pattern path at which each of delay times of said control signal propagating therein is minimized and dividing the binary-tree-shaped wiring pattern path into multi-stage hierarchical sub-trees; calculating delay times of said control signal propagating from each of said branch nodes to each of said leaf nodes, said calculating step being successively repeated from the lowermost ones of said branch nodes to the uppermost one of said branch nodes; setting physical positions of said branch nodes on the semiconductor substrate where a difference among said delay times becomes minimum; updating previous entire information about a circuit connection when said repeating buffer cells are inserted; separating said repeating buffer cells from other cells being overlapped with said repeating buffer cells on said binary-tree-shaped wiring pattern path; correcting arrangement information about positions of all the cells on the semiconductor substrate so as not to have any of the cells being overlapped; and determining a final wiring-pattern path among each of said branch nodes.
Claim 3
Dependent Claim
35 words
A control signal distributing method as claimed in claim 1, wherein one of a clock signal, a data set signal, a data reset signal and a chip enable signal is used as said control signal.
Claim 4
Dependent Claim
44 words
A control signal distributing method as claimed in claim 1, wherein said delay times are defined by resistance values and capacitance values of a signal path from each of said branch nodes of said binary-tree-shaped wiring pattern path to each of said leaf nodes.
Claim 5
Dependent Claim
128 words
A control signal distributing method as claimed in claim 1, wherein each of said inserting portions of said repeating buffer cells is initially set to a position of the highest one of said branch nodes belonging to each of said sub-trees at each buffering stage; thereafter said position is modified to a position where said delay time therefrom to said leaf nodes is equal to the largest one of said delay times that is one of said repeating buffer cells having been inserted into the same stage of said multi-stage hierarchical sub-trees on said binary-tree-shaped wiring pattern path; and a direction of modification of said position is that of approaching a repeating buffer cell in a brother/sister relationship with one of said repeating buffer cells to be modified.
Claim 6
Dependent Claim
71 words
A control signal distributing method as claimed in claim 3, wherein a calculation is performed to obtain a maximum upper limit value from a plurality of upper limit values of a tree-depth of said multi-stage hierarchical sub-trees which are driven by available sorts of said repeating buffer cells, and thereafter a minimum stage number of said repeating buffer cells to be inserted is calculated based on said maximum upper limit value.
Claim 7
Dependent Claim
235 words
A control signal distributing method as claimed in claim 1, wherein said step of determining a final wiring-pattern path among each of said branch nodes includes the steps of: connecting one of said branch nodes as a parent node on said binary-tree-shaped wiring pattern path to each of two of said branch nodes which are adjacent downward to said parent node as child nodes; rearranging a position of said parent node with regard to each of said child nodes to a position on said final wiring-pattern path that a first difference of delay from said parent node to each of said leaf nodes descendant from said parent node via said each of child nodes becomes minimum; determining another final wiring-pattern path up to the topmost branch node within one of said multi-stage hierarchical sub-trees by repeating said rearranging step from a side of a descendant one of said leaf nodes upward to the topmost branch node; and forming a detour path portion within said another final wiring-pattern path from the topmost branch node of one of said multi-stage hierarchical sub-trees to a branch node upward that is to directly drive said one of said sub-trees, where said detour path portion conforms to a delay time in signal propagation along a downstream direction of said one of said sub-trees to that of a multi-stage hierarchical sub-tree of the same stage which has a maximum delay time.
Claim 8
Dependent Claim
47 words
A control signal distributing method as claimed in claim 1, wherein when determining said final wiring-pattern path, a position of a cell through which said final wiring-pattern path is not permitted to pass is modified to a position where said final wiring-pattern path is permitted to pass.
Claim 9
Dependent Claim
77 words
A control signal distributing method as claimed in claim 1, wherein at least a portion of the binary-tree-shaped wiring pattern path used to distribute the control signal, except for a portion of the wiring pattern path formed within said clusters, is formed with employment of a wiring pattern layer specific to the control signal, having a wire resistance value and a wire load capacitance value smaller than those of said wiring pattern path formed within said clusters.
Claim 10
Dependent Claim
150 words
A control signal distributing method as claimed in claim 1, wherein said physical positions of said branch nodes on the semiconductor substrate are determined to be positioned where a first sum consisting of a first delay time from one of said branch nodes as a parent node to one, as one child node, of said two branch nodes adjacent downward to said parent node plus a second delay time from said one child node to the lowermost one among said leaf nodes which are descendants of said one child node is equal to a second sum consisting of a third delay time from said parent node to another one, as another child node, of said two branch nodes adjacent downward to said parent node plus a fourth delay time from said another child node to the lowermost one among said leaf nodes which are descendants of said another child node.
Claim 11
Dependent Claim
99 words
A control signal distributing method as claimed in claim 1, wherein, at a depth of each one of said sub-trees driven by one of said repeating buffer cells, judging whether or not an estimated delay time of a control signal propagation from said depth downward to any one of end positions is shortened by inserting another repeating buffer cell at a downward position of said depth and, in the case of being shortened, inserting said another repeating buffer cell into a position where a delay time of said control signal propagating through the binary-tree-shaped wiring pattern path is minimized.
Claim 12
Dependent Claim
12 words
A semiconductor integrated circuit produced through said method claimed in claim 1.
Claim 13
Independent Claim
153 words
A method for distributing a control signal in a wiring-pattern network formed on a semiconductor substrate, wherein said control signal is supplied from a root driver cell to a plurality of terminal cells, the method comprising the steps of: forming a binary-tree-shaped wiring pattern path connecting between said root driver cell and said terminal cells, wherein said root driver cell is constituted as a root node and said terminal cells are constituted as leaf nodes; determining a position of a branch node on said binary-tree-shaped wiring pattern path to a point where a difference between delay times each of which is taken for said control signal to propagate from said branch node downward to each of descendant leaf nodes in said leaf nodes is minimized; and repeating said determining step of said position of said branch node successively from a side of said leaf nodes upward to a side of said root node.
Claim 14
Independent Claim
153 words
A method for distributing a control signal in a wiring-pattern network formed on a semiconductor substrate, wherein said control signal is supplied from a root driver cell to a plurality of terminal cells, the method comprising the steps of: forming a binary-tree-shaped wiring pattern path connecting between said root driver cell and said terminal cells, wherein said root driver cell is constituted as a root node and said terminal cells are constituted as leaf nodes; determining a position of a branch node on said binary-tree-shaped wiring pattern path to a point where a difference between delay times each of which is taken for said control signal to propagate from said branch node downward to each of descendant leaf nodes in said leaf nodes is minimized; and repeating said determining step of said position of said branch node successively from a side of said leaf nodes upward to a side of said root node.
Claim 15
Dependent Claim
45 words
A method for distributing a control signal as claimed in claim 12, wherein said delay times are defined by resistance values and capacitance values of a signal path from said branch node of said binary-tree-shaped wiring pattern path to each of said descendant leaf nodes.
Claim 16
Dependent Claim
35 words
A control signal distributing method as claimed in claim 12, wherein one of a clock signal, a data set signal, a data reset signal and a chip enable signal is used as said control signal.
Claim 17
Dependent Claim
12 words
A semiconductor integrated circuit produced through said method claimed in claim 12.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-17 | 2000-03-18 | 2000-09-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-17 | 2004-03-18 | 2004-09-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-17 | 2008-03-18 | 2008-09-17 | $7700.00 | Window Closed / Lapsed |