Representation and processing of hierarchical block designs

Claim 2

In a computer aided engineering system, a method of determining at least one parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of: (a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected; (b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design; (c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said parameter; and (d) providing an indication of the result of step (c).

Claim 3

Method of claim 1 wherein said parameter to be determined is a delay parameter associated with each leaf component.

Claim 4

Method of claim 2 wherein step (b) further comprises: (i) determining a gate count ("G L ") for each leaf component represented in the data structure; (ii) calculating a gate count ("G NL ") for each nonleaf component represented in the data structure; (iii) determining a connection count ("N L ") and pin capacitance ("C L ") for each port of each leaf component represented in the data structure; (iv) calculating a connection count ("N NL ") and pin capacitance ("C NL ") for each net represented in the data structure; (v) determining a connection count ("N NPL ") and pin capacitance ("C NLP ") for each port of each nonleaf component represented in the data structure; (vi) determining an intrinsic capacitance ("I") for each net represented in the data structure; and (vii) determining a total capacitance ("T") for each net represented in the data structure.

Claim 5

Method of claim 3 wherein G L is predefined.

Claim 6

Method of claim 3 wherein G NL for each nonleaf component is equal to the sum of the gate counts G L Of all leaf components listed in the block for which the synthesis is to be performed.

Claim 7

Method of claim 3 wherein the connection count N L and pin capacitance C L for each port of each leaf block is predefined.

Claim 8

Method of claim 3 wherein the connection count N NL for each net is equal to the sum of the connection counts N L of all ports connected to the net for Which N NL is to be calculated.

Claim 9

Method of claim 3 wherein the pin capacitance C NL for each net is equal to the sum of the pin capacitances C L of all ports connected to the net for Which C NL is to be calculated.

Claim 10

Method of claim 3 wherein the pin capacitance C NLP for each port of each nonleaf component is equal to the pin capacitance C NL of a net associated with that port.

Claim 11

Method of claim 3 wherein the connection count N NLP for each port of each nonleaf component is equal to the connection count N NL of a net associated with that port.

Claim 12

Method of claim 3 wherein the intrinsic capacitance I of each internal net is a function of at least the values of N NL and G NL associated with that net.

Claim 13

Method of claim 3 wherein the total capacitance T of each net is equal to the sum of C NL and I associated with that net.

Claim 14

Method of claim 2 wherein step (c) further comprises: (i) determining an attribute ("T") associated with each port of each nonleaf component represented by the data structure; and (ii) determining the attribute T associated with each net and port represented in the data structure.

Claim 15

Method of claim 13 wherein T represents the total capacitance.

Claim 16

Method of claim 13 wherein step (c) further comprises: (iii) determining a delay parameter associated with an output port of each leaf component represented in the data structure.

Claim 17

Method of claim 15 wherein step (iii) comprises: (1) determining a maximum capacitance ("C i ") of any net connected to an input port of at least one leaf component; (2) determining a capacitance ("C o ") of an output port of the leaf component for which C i was determined in step (1); and (3) calculating the delay parameter associated with the output port for which C o was determined in step (2), said delay parameter being a function of at least C o and C i .

Claim 18

In a computer aided engineering system, a method of determining at least one parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of: (a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected; (b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design, the synthesis comprising: (i) determining a gate count ("G L ") for each leaf component represented in the data structure; (ii) calculating a gate count ("G NL ") for each nonleaf component represented in the data structure; (iii) determining a connection count ("N L ") and pin capacitance ("C L ") for each port of each leaf component represented in the data structure; (iv) calculating a connection count ("N NL ") and pin capacitance ("C NL ") for each net represented in the data structure; (v) determining a connection count ("N NPL ") and pin capacitance ("C NLP ") for each port of each nonleaf component represented in the data structure; (vi) determining an intrinsic capacitance ("I") for each net represented in the data structure; and (vii) determining a total capacitance ("T") for each net represented in the data structure; (c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said parameter; and (d) providing an indication of the result of step (c).

Claim 19

In a computer aided engineering system, a method of determining at least one parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of: (a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected; (b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design, the synthesis comprising: (i) determining a gate count ("G L ") for each leaf component represented in the data structure; (ii) calculating a gate count ("G NL ") for each nonleaf component represented in the data structure; (iii) determining a connection count ("N L ") and pin capacitance ("C L ") for each port of each leaf component represented in the data structure; (iv) calculating a connection count ("N NL ") and pin capacitance ("C NL ") for each net represented in the data structure; (v) determining a connection count ("N NPL ") and pin capacitance ("C NLP ") for each port of each nonleaf component represented in the data structure; (vi) determining an intrinsic capacitance ("I") for each net represented in the data structure; and (vii) determining a total capacitance ("T") for each net represented in the data structure; (c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said parameter; and (d) providing an indication of the result of step (c).

Claim 20

Method of claim 17 wherein G L is predefined.

Claim 21

Method of claim 17 wherein G NL for each nonleaf component is equal to the sum of the gate counts G L of all leaf components represented by the block for Which the synthesis is to be performed.

Claim 22

Method of claim 17 wherein the connection count N L and pin capacitance C L associated with each port of each leaf component is predefined.

Claim 23

Method of claim 17 wherein the connection count N NL for each net is equal to the sum of the connection counts N L of all ports connected to the net for which N NL is to be calculated.

Claim 24

Method of claim 17 wherein the pin capacitance C NL associated with each net is equal to the sum of the pin capacitances C L of all ports connected to the net for which C NL is to be calculated.

Claim 25

Method of claim 17 wherein the pin capacitance C NLP associated with each port of each nonleaf component is equal to the pin capacitance C NL of a net associated with that port.

Claim 26

Method of claim 17 wherein the connection count N NLP associated with each port of each nonleaf block is equal to the connection count N NL of a net associated with that port.

Claim 27

Method of claim 17 wherein the intrinsic capacitance I of each internal net is a function of at least the values of N NL and G NL associated with that net.

Claim 28

Method of claim 17 wherein the total capacitance T of each net is equal to the sum of C NL and I associated with that net.

Claim 29

In a computer aided engineering system, a method of determining a delay parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of: (a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected; (b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design; (c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said delay parameter, the analysis comprising: (i) determining an attribute ("T") associated with each port of each nonleaf component represented by the data structure; and (ii) determining the attribute T associated with each net and port represented in the data structure; and (d) providing an indication of the result of step (c).

Claim 30

In a computer aided engineering system, a method of determining a delay parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of: (a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected; (b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design; (c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said delay parameter, the analysis comprising: (i) determining an attribute ("T") associated with each port of each nonleaf component represented by the data structure; and (ii) determining the attribute T associated with each net and port represented in the data structure; and (d) providing an indication of the result of step (c).

Claim 31

Method of claim 27 wherein T represents the total capacitance.

Claim 32

Method of claim 27 wherein step (c) further (iii) determining a delay delay parameter associated with each output port of each leaf component.

Claim 33

Method of claim 29 wherein step (iii) comprises: (1) determining a maximum capacitance ("C i ") of any net connected to any input port of at least one leaf component; (2) determining a capacitance ("C o ") of an output port of the leaf component for which C i was determined in step (1); and (3) calculating the delay parameter associated with the output port for which C o was determined in step (2), said delay parameter being a function of at least C o and C i .

Claim 34

In a computer aided engineering system, a method of determining a delay parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of: (a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected; (b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design, the synthesis comprising: (i) determining a gate count ("G L ") for each leaf component represented in the data structure; (ii) calculating a gate count ("G NL ") for each nonleaf component represented in the data (iii) determining a connection count ("N L ") and pin capacitance ("C L ") for each port of each leaf component represented in the data structure; (iv) calculating a connection count ("N NL ") and pin capacitance ("C NLP ") for each net represented in the data structure; (v) determining a connection count ("N NPL ") and pin capacitance ("C NLP ") for each port of each nonleaf component represented in the data structure; (vi) determining an intrinsic capacitance ("I") for each net represented in the data structure; and (vii) determining a total capacitance ("T") for each net represented in the data structure; (c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said delay parameter, the analysis comprising: (i) determining an attribute ("T") associated with each port of each nonleaf component represented by the data structure; and (ii) determining the attribute T associated with each net and port represented in the data structure; and (d) providing an indication of the result of step (c).

Claim 35

In a computer aided engineering system, a method of determining a delay parameter associated with a hierarchical circuit design, the hierarchical circuit having at least one nonleaf component, the nonleaf component having at least one leaf component, and each component having at least one input port and one output port, the method comprising the steps of: (a) constructing a data structure representing the hierarchical circuit design, each nonleaf component of the circuit represented in the data structure by a block of data, each block of data comprising (1) a list of ports of the nonleaf component, (2) a list of components composing said nonleaf component, and (3) a partitioned list of ports of said components composing said nonleaf component, said partitioned list of ports being partitioned into classes representing nets to which said ports are connected; (b) synthesizing, based at least upon the data structure constructed in step (a), a list of attributes associated with each block in the design, the synthesis comprising: (i) determining a gate count ("G L ") for each leaf component represented in the data structure; (ii) calculating a gate count ("G NL ") for each nonleaf component represented in the data (iii) determining a connection count ("N L ") and pin capacitance ("C L ") for each port of each leaf component represented in the data structure; (iv) calculating a connection count ("N NL ") and pin capacitance ("C NLP ") for each net represented in the data structure; (v) determining a connection count ("N NPL ") and pin capacitance ("C NLP ") for each port of each nonleaf component represented in the data structure; (vi) determining an intrinsic capacitance ("I") for each net represented in the data structure; and (vii) determining a total capacitance ("T") for each net represented in the data structure; (c) analyzing, based at least upon the list of attributes synthesized in step (b), the data structure and determining said delay parameter, the analysis comprising: (i) determining an attribute ("T") associated with each port of each nonleaf component represented by the data structure; and (ii) determining the attribute T associated with each net and port represented in the data structure; and (d) providing an indication of the result of step (c).

Claim 36

Method of claim 31 wherein G L is predefined.

Claim 37

Method of claim 31 wherein G NL associated with each nonleaf component is equal to the sum of the gate counts G L of all leaf components represented by the block for which the synthesis is to be performed.

Claim 38

Method of claim 31 wherein the connection count N L and pin capacitance C L for each port of each leaf component is predefined.

Claim 39

Method of claim 31 wherein the connection count N NL for each net is equal to the sum of the connection counts N L of all ports connected to the net for which N NL is to be calculated.

Claim 40

Method of claim 31 wherein the pin capacitance C NL for each net is equal to the sum of the pin capacitances C L of all ports connected to the net for which C NL is to be calculated.

Claim 41

Method of claim 31 wherein the pin capacitance C NLP for each port of each nonleaf component is equal to the pin capacitance C NL of a net associated with that port.

Claim 42

Method of claim 31 wherein the connection count N NLP for each port of each nonleaf component is equal to the connection count N NL of a net associated with that port.

Claim 43

Method of claim 31 wherein the intrinsic capacitance I is a function of at least the values of N NL and G NL associated with the net for which I is to be determined.

Claim 44

Method of claim 31 wherein the total capacitance T of each net is equal to the sum of C NL and I associated with that net.

Claim 45

Method of claim 31 wherein step (c) further comprises: (iii) determining a delay delay parameter associated with each output port of each leaf component.

Claim 46

Method of claim 41 wherein step (iii) comprises: (1) determining a maximum capacitance ("C i ") of any net connected to an input port of at least (2) determining a capacitance ("C o ") of an output port of the leaf component for which C i was determined in step (1); and (3) calculating the delay parameter associated with the output port for which C o was determined in step (2), said delay parameter being a function of at least C o and C i .

Claim 47

Method of claim 31 wherein the data structure constructed in step (a) further comprises: (4) a list of types indicative of the respective functions performed by the components comprising the nonleaf block.