Flip-flop with full scan capability

Claim 2

A circuit comprising: a first switch having a control lead, an input lead and an output lead, wherein said control lead of said first switch is adapted to receive a first clock signal, and said input lead of said first switch is adapted to receive a first data signal; a master stage having an input lead and an output lead, said input lead of said first stage coupled to said output lead of said first switch, wherein said master stage is capable of storing a logic value dependent on a logic state of a master-in signal received at said input lead of said master stage and of outputting a master-out signal at said output lead of said master stage having a logic state dependent on said logic value stored in said master stage; a second switch having a control lead, an input lead and an output lead, wherein said control lead of said second switch is adapted to receive a second clock signal, said input lead of said second switch is adapted to receive a second data signal, and said output lead of said second switch is coupled to said input lead of said master stage; a third switch having a control lead, an input lead and an output lead, wherein said control lead of said third switch is adapted to receive said first clock signal, and said input lead of said third switch is coupled to said output lead of said master stage; a slave stage having an input lead and an output lead, said input lead of said slave stage coupled to said output lead of said third switch, wherein said slave stage is capable of storing a logic value dependent on a logic state of said master-out signal provided by said master stage; a fourth switch having a control lead, an input lead and an output lead, wherein said control lead of said fourth stage is adapted to receive said second clock signal, and said input lead of said fourth switch is coupled to said output lead of said third switch; and a first logic gate having an input lead coupled to said output lead of said fourth switch.

Claim 3

The circuit of claim 1 wherein responsive to said first clock signal said first switch closes when said third switch opens and opens when said third switch closes.

Claim 4

The circuit of claim 1 wherein responsive to said second clock signal said second switch closes when said fourth switch opens and opens when said fourth switch closes.

Claim 5

The circuit of claim 1 wherein said first logic gate is an inverter.

Claim 6

The circuit of claim 1 wherein said first switch comprises: a p-channel field effect transistor (FET) having a gate and a channel, wherein said channel of said p-channel FET of said first switch couples said input lead of said first switch to said output lead of said first switch, and said gate of said p-channel FET of said first switch is coupled to receive said first clock signal; and a n-channel FET having a gate and a channel, wherein said channel of said n-channel FET of said first switch couples said input lead of said first switch to said output lead of said first switch, and said gate of said n-channel FET of said first switch is coupled to receive a complemented first clock signal.

Claim 7

The circuit of claim 5 wherein said third switch comprises: a p-channel FET having a gate and a channel, wherein said channel of said p-channel FET of said third switch couples said input lead of said third switch to said output lead of said third switch, and said gate of said p-channel FET of said third switch is coupled to receive said complemented first clock signal; and a n-channel FET having a gate and a channel, wherein said channel of said n-channel FET of said third switch couples said input lead of said third switch to said output lead of said third switch, and said gate of said n-channel FET of said third switch is coupled to receive said first clock signal.

Claim 8

The circuit of claim 6 wherein said mater stage comprises two inverters connected back-to-back.

Claim 9

The circuit of claim 7 wherein said slave stage comprises two inverters connected back-to-back.

Claim 10

The circuit of claim 1 wherein said circuit has a first operational mode and a second operation mode.

Claim 11

The circuit of claim 9 wherein said circuit enters said first operational mode in response to said second clock signal remaining in a substantially constant logic state and said first clock signal alternating between logic states and wherein said circuit enters said second operational mode in response to said first clock signal remaining in a substantially constant logic state and said second clock signal alternating between logic states.

Claim 12

The circuit of claim 10 wherein said second switch remains open during said first operational mode and said first switch remains open during said second operational mode.

Claim 13

The circuit of claim 11 wherein, during said first operational mode, said first switch closes during a first part of a clock cycle of said first clock signal causing said first data signal to serve as said master-in signal.

Claim 14

The circuit of claim 11 wherein, during said first operational mode, said third switch opens during a second part of a clock cycle of said first clock signal causing said slave section and said first logic gate to receive said master-out signal provided by said master stage.

Claim 15

The circuit of claim 11 wherein, during said second operational mode, said second switch closes during a first part of a clock cycle of said second clock signal causing said second data signal to serve as said master-in signal.

Claim 16

The circuit of claim 11 wherein, during said second operational mode, said fourth switch opens during a second part of a clock cycle of said second clock signal causing first logic gate to receive said master-out signal provided by said master stage.

Claim 17

The circuit of claim 1 further comprising a second logic gate coupling said output lead of said third switch to said input lead of said fourth switch.

Claim 18

The circuit of claim 16 wherein said second logic gate comprises an inverter.

Claim 19

A computer system comprising: a memory; an interface capable of interfacing with one or more peripherals; and a processor coupled to said memory and said interface, said processor including a circuit comprising: a first switch having a control lead, an input lead and an output lead, wherein said control lead of said first switch is adapted to receive a first clock signal, and said input lead of said first switch is adapted to receive a first data signal; a master stage having an input lead and an output lead, said input lead of said first stage coupled to said output lead of said first switch, wherein said master stage is capable of storing a logic value dependent on a logic state of a master-in signal received at said input lead of said master stage and of outputting a master-out signal at said output lead of said master stage having a logic state dependent on said logic value stored in said master stage; a second switch having a control lead, an input lead and an output lead, wherein said control lead of said second switch is adapted to receive a second clock signal, said input lead of said second switch is adapted to receive a second data signal, and said output lead of said second switch is coupled to said input lead of said master stage; a third switch having a control lead, an input lead and an output lead, wherein said control lead of said third switch is adapted to receive said first clock signal, and said input lead of said third switch is coupled to said output lead of said master stage; a slave stage having an input lead and an output lead, said input lead of said slave stage coupled to said output lead of said third switch, wherein said slave stage is capable of storing a logic value dependent on a logic state of said master-out signal provided by said master stage; a fourth switch having a control lead, an input lead and an output lead, wherein said control lead of said fourth stage is adapted to receive said second clock signal, and said input lead of said fourth switch is coupled to said output lead of said third switch; and a first logic gate having an input lead coupled to said output lead of said fourth switch.

Claim 20

A computer system comprising: a memory; an interface capable of interfacing with one or more peripherals; and a processor coupled to said memory and said interface, said processor including a circuit comprising: a first switch having a control lead, an input lead and an output lead, wherein said control lead of said first switch is adapted to receive a first clock signal, and said input lead of said first switch is adapted to receive a first data signal; a master stage having an input lead and an output lead, said input lead of said first stage coupled to said output lead of said first switch, wherein said master stage is capable of storing a logic value dependent on a logic state of a master-in signal received at said input lead of said master stage and of outputting a master-out signal at said output lead of said master stage having a logic state dependent on said logic value stored in said master stage; a second switch having a control lead, an input lead and an output lead, wherein said control lead of said second switch is adapted to receive a second clock signal, said input lead of said second switch is adapted to receive a second data signal, and said output lead of said second switch is coupled to said input lead of said master stage; a third switch having a control lead, an input lead and an output lead, wherein said control lead of said third switch is adapted to receive said first clock signal, and said input lead of said third switch is coupled to said output lead of said master stage; a slave stage having an input lead and an output lead, said input lead of said slave stage coupled to said output lead of said third switch, wherein said slave stage is capable of storing a logic value dependent on a logic state of said master-out signal provided by said master stage; a fourth switch having a control lead, an input lead and an output lead, wherein said control lead of said fourth stage is adapted to receive said second clock signal, and said input lead of said fourth switch is coupled to said output lead of said third switch; and a first logic gate having an input lead coupled to said output lead of said fourth switch.

Claim 21

The circuit of claim 18 wherein responsive to said first clock signal said first switch closes when said third switch opens and opens when said third switch closes.

Claim 22

The circuit of claim 18 wherein responsive to said second clock signal said second switch closes when said fourth switch opens end opens when said fourth switch closes.

Claim 23

The circuit of claim 18 wherein said first logic gate is an inverter.

Claim 24

The circuit of claim 18 wherein said first switch comprises: a p-channel field effect transistor (FET) having a gate and a channel, wherein said channel of said p-channel FET of said first switch couples said input lead of said first switch to said output lead of said first switch, and said gate of said p-channel FET of said first switch is coupled to receive said first clock signal; and a n-channel FET having a gate and a channel, wherein said channel of said n-channel FET of said first switch couples said input lead of said first switch to said output lead of said first switch, and said gate of said n-channel FET of said first switch is coupled to receive a complemented first clock signal.

Claim 25

The circuit of claim 22 wherein said third switch comprises: a p-channel FET having a gate and a channel, wherein said channel of said p-channel FET of said third switch couples said input lead of said third switch to said output lead of said third switch, and said gate of said p-channel FET of said third switch is coupled to receive said complemented first clock signal; and a n-channel FET having a gate and a channel, wherein said channel of said n-channel FET of said third switch couples said input lead of said third switch to said output lead of said third switch, and said gate of said n-channel FET of said third switch is coupled to receive said first clock signal.

Claim 26

The circuit of claim 23 wherein said master stage comprises two inverters connected back-to-back.

Claim 27

The circuit of claim 24 wherein said slave stage comprises two inverters connected back-to-back.

Claim 28

The circuit of claim 18 wherein said circuit has a first operational mode and a second operation mode.

Claim 29

The circuit of claim 26 wherein said circuit enters said first operational mode in response to said second clock signal remaining in a substantially constant logic state and said first clock signal alternating between logic states and wherein said circuit enters said second operational mode in response to said first clock signal remaining in a substantially constant logic state and said second clock signal alternating between logic states.

Claim 30

The circuit of claim 27 wherein said second switch remains open during said first operational mode and said first switch remains open during said second operational mode.

Claim 31

The circuit of claim 28 wherein, during said first operational mode, said first switch closes during a first part of a clock cycle of said first clock signal causing said first data signal to serve as said master-in signal.

Claim 32

The circuit of claim 28 wherein, during said first operational mode, said third switch opens during a second part of a clock cycle of said first clock signal causing said slave section and said first logic gate to receive said master-out signal provided by said master stage.

Claim 33

The circuit of claim 28 wherein, during said second operational mode, said second switch closes during a first part of a clock cycle of said second clock signal causing said second data signal to serve as said master-in signal.

Claim 34

The circuit of claim 28 wherein, during said second operational mode, said fourth switch opens during a second part of a clock cycle of said second clock signal causing first logic gate to receive said master-out signal provided by said master stage.

Claim 35

The circuit of claim 18 further comprising a second logic gate coupling said output lead of said third switch to said input lead of said fourth switch.

Claim 36

The circuit of claim 33 wherein said second logic gate comprises an inverter.