US6310386B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
High performance chip/package inductor integration
Assignee: Koninklijke Philips NV
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Filing: 1998-12-17
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Granted: 2001-10-30
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Expires: 2018-12-17
Abstract
Abstract A packaged semiconductor circuit for use in processing digital and RF signals. The packaged semiconductor circuit includes a package structure having a first side that includes a metallization layer. The metallization layer has a first part at about a center of the first side and a second part that surrounds the center. The circuit further includes a semiconductor die that is attached to the package structure at about the first part of the metallization layer. The semiconductor die has an interconnection side including an array of bumps that are configured to make electrical connection to selected ones of a first plurality of metallization traces that are defined in the first part of the metallization layer of the package structure. The circuit also includes a spiral inductor trace that is formed from the metallization layer of the package structure and is defined in the first part of the metallization layer. And, selected ones of the array of bumps are electrically interconnected to a first end of the spiral inductor trace and to a second end of the spiral inductor trace, such that selected ones of the array of bumps electrically interconnect the spiral inductor trace of the package structure to the semiconductor die and to selected ones of the first plurality of metallization traces. Furthermore, spiral inductor that is part of the package structure has a significantly improved quality factor "Q" and self-resonant frequency compared to a die fabricated inductor.
Inventors
- 👤 Jayarama N. Shenoy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:56
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/501; H10W72/00; H10W44/20; H10W44/241; H10W44/248; H10W90/00; H10W90/701; H10W90/721; H10W90/724; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49204; Y10T29/49208; Y10T29/49222
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
157 words
A digital and radio frequency (RF) circuit, comprising: a package structure having a first side that includes a metallization layer, the metallization layer is divided into a first part and a second part; a semiconductor die having integrated circuitry being attached to the package structure such that the semiconductor die overlies a portion of the first part of the metallization layer and a portion of the second part, the semiconductor die having an interconnection side including an array of bumps that are configured to make electrical connection to selected ones of a first plurality of metallization traces that are defined in the first part of the metallization layer of the package structure; and a spiral inductor trace defined from the metallization layer of the package structure, the spiral inductor trace defined from the first part of the metallization layer, and selected ones of the array of bumps electrically interconnect the spiral inductor trace to the semiconductor die.
Claim 2
Dependent Claim
157 words
A digital and radio frequency (RF) circuit, comprising: a package structure having a first side that includes a metallization layer, the metallization layer is divided into a first part and a second part; a semiconductor die having integrated circuitry being attached to the package structure such that the semiconductor die overlies a portion of the first part of the metallization layer and a portion of the second part, the semiconductor die having an interconnection side including an array of bumps that are configured to make electrical connection to selected ones of a first plurality of metallization traces that are defined in the first part of the metallization layer of the package structure; and a spiral inductor trace defined from the metallization layer of the package structure, the spiral inductor trace defined from the first part of the metallization layer, and selected ones of the array of bumps electrically interconnect the spiral inductor trace to the semiconductor die.
Claim 3
Dependent Claim
42 words
A digital and radio frequency (RF) circuit as recited in claim 1 , further comprising: an input signal terminal defined at a first end of the spiral inductor; and an output signal terminal defined at a second end of the spiral inductor.
Claim 4
Dependent Claim
64 words
A digital and radio frequency (RF) circuit as recited in claim 2 , further comprising: a plurality of interconnecting traces defined from the metallization layer, such that selected ones of the plurality of interconnecting traces provide a power source, selected ones provide a ground source, and selected ones provide signals to and from the semiconductor die through selected ones of the array of bumps.
Claim 5
Dependent Claim
38 words
A digital and radio frequency (RF) circuit as recited in claim 1 , further comprising: an array of solder balls being coupled to the second part of the metallization layer of the first side of the package structure.
Claim 6
Dependent Claim
44 words
A digital and radio frequency (RF) circuit as recited in claim 4 , further comprising: a second plurality of metallization traces defined on the second part of the metallization layer and configured to electrically connect to selected ones of the array of solder balls.
Claim 7
Dependent Claim
78 words
A digital and radio frequency (RF) circuit as recited in claim 5 , wherein selected ones of the first plurality of metallization traces integrally interconnect to selected ones of the second plurality of metallization traces, thereby providing electrical connections between the array of solder balls coupled to the second part and the array of bumps coupled to the semiconductor die that lies over at least a portion of the first part and a portion of the second part.
Claim 8
Dependent Claim
63 words
A digital and radio frequency (RF) circuit as recited in claim 1 , further comprising: metallization layer defined on a second side of the package structure, the metallization layer having a plurality of conductive traces; and an array of solder balls coupled to selected ones of the plurality of conductive traces of the metallization layer of the second side of the package structure.
Claim 9
Dependent Claim
64 words
A digital and radio frequency (RF) circuit as recited in claim 7 , further comprising: a plurality of conductive vias for interconnecting the metallization layer of the first side of the package structure to the second side of the package structure, and selected ones of the array of solder balls configured to make electrical interconnection to the array of bumps of the semiconductor die.
Claim 10
Dependent Claim
24 words
A digital and radio frequency (RF) circuit as recited in claim 2 , wherein the spiral inductor trace is implemented in RF signal processing.
Claim 11
Dependent Claim
32 words
A digital and radio frequency (RF) circuit as recited in claim 1 , wherein the package structure is one of a tape-based flip-chip package, a plastic core package, and a laminate package.
Claim 12
Dependent Claim
26 words
A digital and radio frequency (RF) circuit as recited in claim 1 , further comprising: integrating the digital and RF circuit into an electronic communication device.
Claim 13
Dependent Claim
31 words
A digital and radio frequency (RF) circuit as recited in claim 11 , wherein the electronic communication device is a cellular telephone, a pager, a home RF network, and a radio.
Claim 14
Dependent Claim
222 words
A packaged semiconductor circuit, comprising: a package structure having a first side that includes a metallization layer, the metallization layer has a first part at about a center of the first side and a second part that surrounds the center; a semiconductor die having integrated circuitry is attached to the package structure at about the first part of the metallization layer such that the semiconductor die overlies a portion of the first part of the metallization layer and at least a portion of the second part of the metallization layer, the semiconductor die having an interconnection side including an array of bumps that are configured to make electrical connection to selected ones of a first plurality of metallization traces that are defined in the first part of the metallization layer of the package structure; and a spiral inductor trace defined from the metallization layer of the package structure, and defined in the first part of the metallization layer, and selected ones of the array of bumps being electrically interconnected to a first end of the spiral inductor trace and to a second end of the spiral inductor trace, such that selected ones of the array of bumps electrically interconnect the spiral inductor trace of the package structure to the semiconductor die and to selected ones of the first plurality of metallization traces.
Claim 15
Dependent Claim
222 words
A packaged semiconductor circuit, comprising: a package structure having a first side that includes a metallization layer, the metallization layer has a first part at about a center of the first side and a second part that surrounds the center; a semiconductor die having integrated circuitry is attached to the package structure at about the first part of the metallization layer such that the semiconductor die overlies a portion of the first part of the metallization layer and at least a portion of the second part of the metallization layer, the semiconductor die having an interconnection side including an array of bumps that are configured to make electrical connection to selected ones of a first plurality of metallization traces that are defined in the first part of the metallization layer of the package structure; and a spiral inductor trace defined from the metallization layer of the package structure, and defined in the first part of the metallization layer, and selected ones of the array of bumps being electrically interconnected to a first end of the spiral inductor trace and to a second end of the spiral inductor trace, such that selected ones of the array of bumps electrically interconnect the spiral inductor trace of the package structure to the semiconductor die and to selected ones of the first plurality of metallization traces.
Claim 16
Dependent Claim
47 words
A packaged semiconductor circuit as recited in claim 13 , wherein a plurality of the spiral inductors are defined in the first part of the metallization layer and under the semiconductor die, such that the semiconductor die is electrically interconnected to the plurality of the spiral inductors.
Claim 17
Dependent Claim
23 words
A packaged semiconductor circuit as recited in claim 14 , wherein the plurality of the spiral inductors are implemented for RF signal processing.
Claim 18
Dependent Claim
18 words
A packaged semiconductor circuit as recited in claim 15 , wherein the semiconductor chip is a CMOS chip.
Claim 19
Dependent Claim
30 words
A packaged semiconductor circuit as recited in claim 13 , wherein the spiral inductor has an improved quality factor “Q” and an increased self-resonant frequency relative to chip fabricated inductors.
Claim 20
Dependent Claim
22 words
A packaged semiconductor circuit as recited in claim 17 , wherein the improved quality factor “Q” can range up to about 180.
Claim 21
Dependent Claim
22 words
A packaged semiconductor circuit as recited in claim 18 , wherein the improved quality factor “Q” can range up to about 80.
Claim 22
Dependent Claim
20 words
A packaged semiconductor circuit as recited in claim 17 , wherein the self-resonant frequency ranges up to about 18 GHz.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-10-29 | 2005-04-30 | 2005-10-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-10-29 | 2009-04-30 | 2009-10-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-10-29 | 2013-04-30 | 2013-10-30 | $7700.00 | Window Closed / Lapsed |