US5747870A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-chip module inductor structure
Assignee: Microchip Technology Caldicot Ltd
•
Filing: 1995-06-08
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Granted: 1998-05-05
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Expires: 2015-06-08
Abstract
Abstract In a multichip module structure comprising a silicon, alumina or sapphire substrate carrying a plurality of layers of metallisation separated by polymer dielectric layers, with one or more inductors formed in the uppermost metallisation layer, a ferrite core for one of those inductors is located over the inductor and secured in position by flip chip solder bonding.
Inventors
- 👤 David John Pedder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:25
CPC Classifications
H; H01; H01F; H01F17/00; H01F17/0006; H01F17/04; H10; H10W; H10W90/00; H10W90/701; H10W90/721; H10W90/724
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
136 words
A multi-chip module inductor structure, comprising: a substantially planar substrate of electrically insulating material; a multilayer metallization/insulation structure formed on said substrate and comprising at least a lower metallization layer, a layer of electrically insulating material formed over said lower metallization layer, and an upper metallization layer formed over said layer of electrically insulating material; an inductor defined in at least said upper metallization layer; a substantially planar chip of ferrite material having upper and lower major surfaces; a plurality of solder bond pads defined in said upper metallization layer and a like plurality of solder bond pads formed on said lower major surface of said chip of ferrite material; and means, including a like plurality of solder bump connections, for attaching said chip of ferrite material over said planar inductor and in spaced relationship therewith.
Claim 2
Dependent Claim
136 words
A multi-chip module inductor structure, comprising: a substantially planar substrate of electrically insulating material; a multilayer metallization/insulation structure formed on said substrate and comprising at least a lower metallization layer, a layer of electrically insulating material formed over said lower metallization layer, and an upper metallization layer formed over said layer of electrically insulating material; an inductor defined in at least said upper metallization layer; a substantially planar chip of ferrite material having upper and lower major surfaces; a plurality of solder bond pads defined in said upper metallization layer and a like plurality of solder bond pads formed on said lower major surface of said chip of ferrite material; and means, including a like plurality of solder bump connections, for attaching said chip of ferrite material over said planar inductor and in spaced relationship therewith.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-04 | 2001-11-03 | 2002-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-04 | 2005-11-03 | 2006-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-04 | 2009-11-03 | 2010-05-05 | $7700.00 | Window Closed / Lapsed |