Patent US6300172B1 successfully refreshed from Google Patents.
US6300172B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of field isolation in silicon-on-insulator technology
Assignee: GlobalFoundries Singapore Pte Ltd
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Filing: 1999-10-01
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Granted: 2001-10-09
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Expires: 2019-10-01
Abstract
Abstract A method of fabricating an SOI transistor device comprises the following steps. a silicon semiconductor structure is provided. A silicon oxide layer is formed over the silicon semiconductor structure. A silicon-on-insulator layer is formed over the oxide layer. A well is implanted in the silicon-on-insulator layer. A gate oxide layer is grown over the silicon-on-insulator layer. A polysilicon layer is deposited over the gate oxide layer. The polysilicon layer, gate oxide layer, and silicon oxide layer are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised shallow trench isolation regions (STIs). The polysilicon layer is patterned and the non-gate portions are removed polysilicon adjacent the raised STIs forming a gate conductor between the raised STIs with the gate conductor and said raised STIs having exposed sidewalls. The gate oxide layer is removed between the gate conductor and the raised STIs, and outboard of the raised STIs. The source and drain are formed in the silicon-on-insulator layer adjacent the gate spacers. Silicide regions may then be formed on the source and drain.
Inventors
- 👤 Ting Cheong Ang
- 👤 Shyue Pong Quek
- 👤 Lap Chan
- 👤 Sang Yee Loong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:27
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10W10/011; H10W10/012; H10W10/13
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
222 words
A method of fabricating an SOI transistor device, comprising the sequential steps of: providing a silicon semiconductor structure; forming a silicon oxide layer over said silicon semiconductor structure; forming a silicon-on-insulator layer over said silicon oxide layer; implanting a well in said silicon-on-insulator layer; growing a gate oxide layer over said silicon-on-insulator layer; depositing a polysilicon layer over said gate oxide layer; patterning and etching said polysilicon layer, said gate oxide layer, and said silicon-on-insulator layer to form trenches exposing a portion of said silicon oxide layer; filling said trenches only with an isolation material to at least a level even with a top surface of said polysilicon layer to form raised shallow trench isolation regions (STIs); patterning said polysilicon layer to remove portions of said polysilicon layer adjacent said raised STIs and to form a gate conductor comprised of a portion of said polysilicon layer between said raised STIs; said gate conductor and said raised STIs having exposed sidewalls; removing said gate oxide layer between said gate conductor and said raised STIs, and outboard of said raised STIs; forming isolation spacers on said exposed sidewalls of said raised STIs and gate spacers on said exposed sidewalls of said gate conductor; forming source and drain in said silicon-on-insulator layer adjacent said gate spacers; and forming silicide regions on said source and drain.
Claim 2
Independent Claim
222 words
A method of fabricating an SOI transistor device, comprising the sequential steps of: providing a silicon semiconductor structure; forming a silicon oxide layer over said silicon semiconductor structure; forming a silicon-on-insulator layer over said silicon oxide layer; implanting a well in said silicon-on-insulator layer; growing a gate oxide layer over said silicon-on-insulator layer; depositing a polysilicon layer over said gate oxide layer; patterning and etching said polysilicon layer, said gate oxide layer, and said silicon-on-insulator layer to form trenches exposing a portion of said silicon oxide layer; filling said trenches only with an isolation material to at least a level even with a top surface of said polysilicon layer to form raised shallow trench isolation regions (STIs); patterning said polysilicon layer to remove portions of said polysilicon layer adjacent said raised STIs and to form a gate conductor comprised of a portion of said polysilicon layer between said raised STIs; said gate conductor and said raised STIs having exposed sidewalls; removing said gate oxide layer between said gate conductor and said raised STIs, and outboard of said raised STIs; forming isolation spacers on said exposed sidewalls of said raised STIs and gate spacers on said exposed sidewalls of said gate conductor; forming source and drain in said silicon-on-insulator layer adjacent said gate spacers; and forming silicide regions on said source and drain.
Claim 3
Dependent Claim
52 words
The method of claim 1 , further including the steps of: forming a threshold voltage implant in said silicon-on-insulator layer before said gate oxide layer growth step; and doping said source and drain forming low doped regions outward of said gate conductor and heavy doped regions outward of said low doped regions.
Claim 4
Dependent Claim
18 words
The method of claim 1 , wherein said isolation material filling said raised STIs is SiO 2 .
Claim 5
Dependent Claim
19 words
The method of claim 1 , wherein said gate oxide layer is from about 1 to 20 nm thick.
Claim 6
Dependent Claim
18 words
The method of claim 1 , wherein said polysilicon layer is from about 150 to 300 nm thick.
Claim 7
Dependent Claim
17 words
The method of claim 1 , wherein said trenches are from about 100 to 1000 nm wide.
Claim 8
Dependent Claim
57 words
The method of claim 1 , further including the steps of: forming isolation spacers on said exposed sidewalls of said raised STIs and gate spacers on said exposed sidewalls of said gate conductor; wherein said isolation spacers are from about 30 to 200 nm wide and said gate spacers are from about 30 to 200 nm wide.
Claim 9
Independent Claim
229 words
A method of fabricating an SOI transistor device, comprising the sequential steps of: providing a silicon semiconductor structure; forming a silicon oxide layer over said silicon semiconductor structure; forming a silicon-on-insulator layer over said silicon oxide layer; implanting a well in said silicon-on-insulator layer; growing a gate oxide layer over said silicon-on-insulator layer; depositing a polysilicon layer over said gate oxide layer; patterning and etching said polysilicon layer, said gate oxide layer, and said silicon-on-insulator layer to form trenches exposing a portion of said silicon oxide layer; filling said trenches only with an isolation material to at least a level even with a top surface of said polysilicon layer to form raised shallow trench isolation regions (STIs); said isolation material being SiO 2 ; patterning said polysilicon layer to remove portions of said polysilicon layer adjacent said raised STIs and to form a gate conductor comprised of a portion of said polysilicon layer between said raised STIs; said gate conductor and said raised STIs having exposed sidewalls; removing said gate oxide layer between said gate conductor and said raised STIs, and outboard of said raised STIs; forming isolation spacers on said exposed sidewalls of said raised STIs and gate spacers on said exposed sidewalls of said gate conductor; forming source and drain in said silicon-on-insulator layer adjacent said gate spacers; and forming silicide regions on said source and drain.
Claim 10
Independent Claim
229 words
A method of fabricating an SOI transistor device, comprising the sequential steps of: providing a silicon semiconductor structure; forming a silicon oxide layer over said silicon semiconductor structure; forming a silicon-on-insulator layer over said silicon oxide layer; implanting a well in said silicon-on-insulator layer; growing a gate oxide layer over said silicon-on-insulator layer; depositing a polysilicon layer over said gate oxide layer; patterning and etching said polysilicon layer, said gate oxide layer, and said silicon-on-insulator layer to form trenches exposing a portion of said silicon oxide layer; filling said trenches only with an isolation material to at least a level even with a top surface of said polysilicon layer to form raised shallow trench isolation regions (STIs); said isolation material being SiO 2 ; patterning said polysilicon layer to remove portions of said polysilicon layer adjacent said raised STIs and to form a gate conductor comprised of a portion of said polysilicon layer between said raised STIs; said gate conductor and said raised STIs having exposed sidewalls; removing said gate oxide layer between said gate conductor and said raised STIs, and outboard of said raised STIs; forming isolation spacers on said exposed sidewalls of said raised STIs and gate spacers on said exposed sidewalls of said gate conductor; forming source and drain in said silicon-on-insulator layer adjacent said gate spacers; and forming silicide regions on said source and drain.
Claim 11
Dependent Claim
52 words
The method of claim 8 , further including the steps of: forming a threshold voltage implant in said silicon-on-insulator layer before said gate oxide layer growth step; and doping said source and drain forming low doped regions outward of said gate conductor and heavy doped regions outward of said low doped regions.
Claim 12
Dependent Claim
19 words
The method of claim 8 , wherein said gate oxide layer is from about 1 to 20 nm thick.
Claim 13
Dependent Claim
18 words
The method of claim 8 , wherein said polysilicon layer is from about 150 to 300 nm thick.
Claim 14
Dependent Claim
17 words
The method of claim 8 , wherein said trenches are from about 100 to 1000 nm wide.
Claim 15
Dependent Claim
30 words
The method of claim 8 , wherein said isolation spacers are from about 30 to 200 nm wide and said gate spacers are from about 30 to 200 nm wide.
Claim 16
Independent Claim
231 words
A method of fabricating an SOI transistor device, comprising the sequential steps of: providing a silicon semiconductor structure; forming a silicon oxide layer over said silicon semiconductor structure; forming a silicon-on-insulator layer over said silicon oxide layer; implanting a well in said silicon-on-insulator layer; forming a threshold voltage implant in said silicon-on-insulator layer; growing a gate oxide layer over said silicon-on-insulator layer; depositing a polysilicon layer over said gate oxide layer; patterning and etching said polysilicon layer, said gate oxide layer, and said silicon-on-insulator layer to form trenches exposing a portion of said silicon oxide layer; filling said trenches only with an isolation material to at least a level even with a top surface of said polysilicon layer to form raised shallow trench isolation regions (STIs); patterning said polysilicon layer to remove portions of said polysilicon layer adjacent said raised STIs and to form a gate conductor comprised of a portion of said polysilicon layer between said raised STIs; said gate conductor and said raised STIs having exposed sidewalls; removing said gate oxide layer between said gate conductor and said raised STIs, and outboard of said raised STIs; forming isolation spacers on said exposed sidewalls of said raised STIs and gate spacers on said exposed sidewalls of said gate conductor; forming source and drain in said silicon-on-insulator layer adjacent said gate spacers; and forming silicide regions on said source and drain.
Claim 17
Independent Claim
231 words
A method of fabricating an SOI transistor device, comprising the sequential steps of: providing a silicon semiconductor structure; forming a silicon oxide layer over said silicon semiconductor structure; forming a silicon-on-insulator layer over said silicon oxide layer; implanting a well in said silicon-on-insulator layer; forming a threshold voltage implant in said silicon-on-insulator layer; growing a gate oxide layer over said silicon-on-insulator layer; depositing a polysilicon layer over said gate oxide layer; patterning and etching said polysilicon layer, said gate oxide layer, and said silicon-on-insulator layer to form trenches exposing a portion of said silicon oxide layer; filling said trenches only with an isolation material to at least a level even with a top surface of said polysilicon layer to form raised shallow trench isolation regions (STIs); patterning said polysilicon layer to remove portions of said polysilicon layer adjacent said raised STIs and to form a gate conductor comprised of a portion of said polysilicon layer between said raised STIs; said gate conductor and said raised STIs having exposed sidewalls; removing said gate oxide layer between said gate conductor and said raised STIs, and outboard of said raised STIs; forming isolation spacers on said exposed sidewalls of said raised STIs and gate spacers on said exposed sidewalls of said gate conductor; forming source and drain in said silicon-on-insulator layer adjacent said gate spacers; and forming silicide regions on said source and drain.
Claim 18
Dependent Claim
35 words
The method of claim 14 , further including the step of: doping said source and drain forming low doped regions outward of said gate conductor and heavy doped regions outward of said low doped regions.
Claim 19
Dependent Claim
18 words
The method of claim 14 , wherein said isolation material filling said raised STIs is SiO 2 .
Claim 20
Dependent Claim
19 words
The method of claim 14 , wherein said gate oxide layer is from about 1 to 20 nm thick.
Claim 21
Dependent Claim
18 words
The method of claim 14 , wherein said polysilicon layer is from about 150 to 300 nm thick.
Claim 22
Dependent Claim
17 words
The method of claim 14 , wherein said trenches are from about 100 to 1000 nm wide.
Claim 23
Dependent Claim
30 words
The method of claim 14 , wherein said isolation spacers are from about 30 to 200 nm wide and said gate spacers are from about 30 to 200 nm wide.
Claim 24
Independent Claim
217 words
A method of fabricating an SOI transistor device, comprising the sequential steps of: providing a semiconductor structure; forming an oxide layer over said semiconductor structure; forming a silicon-on-insulator layer over said oxide layer; implanting a well in said silicon-on-insulator layer; growing a gate oxide layer over said silicon-on-insulator layer; depositing a polysilicon layer over said gate oxide layer; patterning and etching said polysilicon layer, said gate oxide layer, and said silicon-on-insulator layer to form trenches exposing a portion of said oxide layer; filling said trenches only with an isolation material to at least a level even with a top surface of said polysilicon layer to form raised shallow trench isolation regions (STIs); patterning said polysilicon layer to remove portions of said polysilicon layer adjacent said raised STIs and to form a gate conductor comprised of a portion of said polysilicon layer between said raised STIs; said gate conductor and said raised STIs having exposed sidewalls; removing said gate oxide layer between said gate conductor and said raised STIs, and outboard of said raised STIs; forming isolation spacers on said exposed sidewalls of said raised STIs and gate spacers on said exposed sidewalls of said gate conductor; forming source and drain in said silicon-on-insulator layer proximate said gate conductor; and forming silicide regions on said source and drain.
Claim 25
Independent Claim
217 words
A method of fabricating an SOI transistor device, comprising the sequential steps of: providing a semiconductor structure; forming an oxide layer over said semiconductor structure; forming a silicon-on-insulator layer over said oxide layer; implanting a well in said silicon-on-insulator layer; growing a gate oxide layer over said silicon-on-insulator layer; depositing a polysilicon layer over said gate oxide layer; patterning and etching said polysilicon layer, said gate oxide layer, and said silicon-on-insulator layer to form trenches exposing a portion of said oxide layer; filling said trenches only with an isolation material to at least a level even with a top surface of said polysilicon layer to form raised shallow trench isolation regions (STIs); patterning said polysilicon layer to remove portions of said polysilicon layer adjacent said raised STIs and to form a gate conductor comprised of a portion of said polysilicon layer between said raised STIs; said gate conductor and said raised STIs having exposed sidewalls; removing said gate oxide layer between said gate conductor and said raised STIs, and outboard of said raised STIs; forming isolation spacers on said exposed sidewalls of said raised STIs and gate spacers on said exposed sidewalls of said gate conductor; forming source and drain in said silicon-on-insulator layer proximate said gate conductor; and forming silicide regions on said source and drain.
Claim 26
Dependent Claim
52 words
The method of claim 21 , further including the steps of: forming a threshold voltage implant in said silicon-on-insulator layer before said gate oxide layer growth step; and doping said source and drain forming low doped regions outward of said gate conductor and heavy doped regions outward of said low doped regions.
Claim 27
Dependent Claim
18 words
The method of claim 21 , wherein said isolation material filling said raised STIs is SiO 2 .
Claim 28
Dependent Claim
19 words
The method of claim 21 , wherein said gate oxide layer is from about 1 to 20 nm thick.
Claim 29
Dependent Claim
18 words
The method of claim 21 , wherein said polysilicon layer is from about 150 to 300 nm thick.
Claim 30
Dependent Claim
16 words
The method of claim 21 , wherein said trenches from about 100 to 1000 nm wide.
Claim 31
Dependent Claim
57 words
The method of claim 21 , further including the steps of: forming isolation spacers on said exposed sidewalls of said raised STIs and gate spacers on said exposed sidewalls of said gate conductor; wherein said isolation spacers are from about 30 to 200 nm wide and said gate spacers are from about 30 to 200 nm wide.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-10-08 | 2005-04-09 | 2005-10-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-10-08 | 2009-04-09 | 2009-10-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-10-08 | 2013-04-09 | 2013-10-09 | $7700.00 | Window Closed / Lapsed |