Memory array having a digit line buried in an isolation region and method for forming same

Claim 2

A memory array, comprising: a semiconductor substrate; an isolation trench disposed in the substrate and having first and second opposite sides; a conductor disposed in the trench; a first memory cell disposed in the substrate adjacent to the first side of the trench, the first memory cell being coupled to the conductor; and a second memory cell disposed in the substrate adjacent to the second side of the trench.

Claim 3

The memory array of claim 1 wherein the first memory cell comprises a pair of source/drain regions disposed in the substrate, one of the regions being coupled to the conductor.

Claim 4

The memory array of claim 1, further comprising: the first memory cell including first and second source/drain regions disposed in the substrate; and an electrically conductive strap disposed on the first source/drain region and on the conductor.

Claim 5

The memory array of claim 1 wherein the second memory cell is electrically isolated from the conductor.

Claim 6

A memory array, comprising: a semiconductor substrate; isolation trenches disposed in the substrate; digit lines each disposed within a respective one of the trenches; isolation segments disposed in the substrate between adjacent ones of the trenches; pairs of adjacent memory cells, each pair bordered by a respective pair of isolation segments and a respective pair of isolation trenches, each pair including a shared source/drain region that is disposed in the substrate; and straps that each electrically couple the shared source/drain region of a respective pair of cells to a respective digit line.

Claim 7

A memory array, comprising: a semiconductor substrate; isolation trenches disposed in the substrate; digit lines each disposed within a respective one of the trenches; isolation segments disposed in the substrate between adjacent ones of the trenches; pairs of adjacent memory cells, each pair bordered by a respective pair of isolation segments and a respective pair of isolation trenches, each pair including a shared source/drain region that is disposed in the substrate; and straps that each electrically couple the shared source/drain region of a respective pair of cells to a respective digit line.

Claim 8

The memory array of claim 5, further comprising a dielectric material disposed in the isolation trenches and encapsulating the digit lines, the dielectric material having openings where the straps contact a respective digit line.

Claim 9

The memory array of claim 5 wherein: the digit lines and straps comprise polysilicon; and the isolation segments comprise an oxide.

Claim 10

The memory array of claim 5 wherein: the trenches are substantially parallel to one another; and the isolation segments are substantially parallel to one another and are substantially orthogonal to the trenches.

Claim 11

The memory array of claim 5, further comprising: the memory cells each including, a gate insulator disposed on the substrate and adjacent to the shared source/drain region, and a gate disposed on the gate insulator; and word lines that are coupled to the gates of the memory cells according to a folded-digit-line layout.

Claim 12

A memory circuit, comprising: a semiconductor substrate; substantially parallel isolation trenches that are disposed in the substrate; digit lines that are respectively disposed within the trenches; trench insulators that are disposed within the trenches and on the digit lines, the trench insulators having openings that expose portions of the digit lines; substantially parallel isolation segments that are disposed in the substrate substantially orthogonally to the trenches such that first segments that are adjacent to a first side of a trench are offset approximately half way between second segments that are adjacent to a second side of the trench; active areas that are defined in the substrate and bounded by the trenches and segments; pairs of memory cells that are each disposed in a respective one of the active areas, each pair of cells including a common source/drain region that is disposed in the substrate and that is substantially adjacent to an exposed portion of a respective digit line, each cell of the pair including a gate insulator that is disposed on the substrate and that is substantially contiguous with the common region, each cell of the pair including a gate disposed on the gate insulator; and conductive straps that are each connected between the common source/drain region of a respective pair of memory cells and the exposed portion of the respective digit line.

Claim 13

A memory circuit, comprising: a semiconductor substrate; substantially parallel isolation trenches that are disposed in the substrate; digit lines that are respectively disposed within the trenches; trench insulators that are disposed within the trenches and on the digit lines, the trench insulators having openings that expose portions of the digit lines; substantially parallel isolation segments that are disposed in the substrate substantially orthogonally to the trenches such that first segments that are adjacent to a first side of a trench are offset approximately half way between second segments that are adjacent to a second side of the trench; active areas that are defined in the substrate and bounded by the trenches and segments; pairs of memory cells that are each disposed in a respective one of the active areas, each pair of cells including a common source/drain region that is disposed in the substrate and that is substantially adjacent to an exposed portion of a respective digit line, each cell of the pair including a gate insulator that is disposed on the substrate and that is substantially contiguous with the common region, each cell of the pair including a gate disposed on the gate insulator; and conductive straps that are each connected between the common source/drain region of a respective pair of memory cells and the exposed portion of the respective digit line.

Claim 14

The memory circuit of claim 10 wherein the substrate comprises silicon.

Claim 15

The memory circuit of claim 10, further comprising word lines that are each respectively coupled to memory cells that are adjacent to the first side of a respective trench and to memory cells that are adjacent to the second side of the trench.

Claim 16

The memory circuit of claim 10, further comprising; first word lines that are each respectively coupled only to memory cells that are adjacent to the first side of a respective trench; and second word lines that are each respectively coupled only to memory cells that are adjacent to the second side of the trench.

Claim 17

The memory circuit of claim 10, further comprising substantially straight word lines that are each coupled to a respective row of the memory cells.

Claim 18

The memory circuit of claim 10, further comprising word lines that are each coupled to a respective group of aligned memory cells that form a row.

Claim 19

The memory circuit of claim 10, further comprising word lines that are each coupled to a respective row of the memory cells, the word lines each having a sub-lithographic dimension.

Claim 20

A memory device, comprising: address, data, and command busses; a bank of memory cells arranged in rows and columns, the bank comprising, a semiconductor substrate, an isolation trench disposed in the substrate and having first and second opposite sides, a digit line disposed in the trench, a first memory cell disposed in the substrate adjacent to the first side of the trench, the first memory cell being coupled to the digit line, and a second memory cell disposed in the substrate adjacent to the second side of the trench; an address decoder coupled to the address bus and to the bank; a read/write circuit coupled to the address decoder and to the digit line; a data input/output circuit coupled to the data bus and to the read/write circuit; and a control circuit coupled to the command bus, to the address decoder, to the read/write circuit, and to the data input/output circuit.

Claim 21

A memory device, comprising: address, data, and command busses; a bank of memory cells arranged in rows and columns, the bank comprising, a semiconductor substrate, an isolation trench disposed in the substrate and having first and second opposite sides, a digit line disposed in the trench, a first memory cell disposed in the substrate adjacent to the first side of the trench, the first memory cell being coupled to the digit line, and a second memory cell disposed in the substrate adjacent to the second side of the trench; an address decoder coupled to the address bus and to the bank; a read/write circuit coupled to the address decoder and to the digit line; a data input/output circuit coupled to the data bus and to the read/write circuit; and a control circuit coupled to the command bus, to the address decoder, to the read/write circuit, and to the data input/output circuit.

Claim 22

The memory device of claim 17 wherein the first memory cell comprises a pair of source/drain regions disposed in the substrate, one of the regions being coupled to the digit line.

Claim 23

The memory device of claim 17 wherein the bank further comprises: the first memory cell including first and second source/drain regions disposed in the substrate; and an electrically conductive strap disposed on the first source/drain region of the first memory cell and on a region of the digit line.

Claim 24

The memory device of claim 17 wherein the first and second memory cells comprise dram-type memory cells.

Claim 25

A computer system, comprising: a data input device; a data output device; and computing circuitry coupled to the data input and output devices, the computing circuitry including a memory device that includes, address, data, and command busses, a bank of memory cells arranged in rows and columns, the bank comprising, a semiconductor substrate, an isolation trench disposed in the substrate and having first and second opposite sides, a digit line disposed in the trench, a first memory cell disposed in the substrate adjacent to the first side of the trench, the first memory cell being coupled to the digit line, and a second memory cell disposed in the substrate adjacent to the second side of the trench; an address decoder coupled to the address bus and to the bank, a read/write circuit coupled to the address decoder and to the digit line, a data input/output circuit coupled to the data bus and to the read/write circuit, and a control circuit coupled to the command bus, to the address decoder, to the read/write circuit, and to the data input/output circuit.

Claim 26

A computer system, comprising: a data input device; a data output device; and computing circuitry coupled to the data input and output devices, the computing circuitry including a memory device that includes, address, data, and command busses, a bank of memory cells arranged in rows and columns, the bank comprising, a semiconductor substrate, an isolation trench disposed in the substrate and having first and second opposite sides, a digit line disposed in the trench, a first memory cell disposed in the substrate adjacent to the first side of the trench, the first memory cell being coupled to the digit line, and a second memory cell disposed in the substrate adjacent to the second side of the trench; an address decoder coupled to the address bus and to the bank, a read/write circuit coupled to the address decoder and to the digit line, a data input/output circuit coupled to the data bus and to the read/write circuit, and a control circuit coupled to the command bus, to the address decoder, to the read/write circuit, and to the data input/output circuit.

Claim 27

The computer system of claim 21 wherein the first memory cell comprises a pair of source/drain regions disposed in the substrate, one of the regions being coupled to the digit line.

Claim 28

The computer system of claim 21 wherein the bank further comprises: the first memory cell including first and second source/drain regions disposed in the substrate; and an electrically conductive strap disposed on the first source/drain region of the first memory cell and on the digit line.

Claim 29

A memory array, comprising: a semiconductor substrate; isolation trenches disposed in the substrate; digit lines each disposed within a respective one of the trenches; isolation segments disposed in the substrate between adjacent ones of the trenches; and pairs of adjacent memory cells, each pair bordered by a respective pair of isolation segments and a respective pair of isolation trenches, each pair including a shared source/drain region that is disposed in the substrate and coupled to one of the digit lines.

Claim 30

A memory array, comprising: a semiconductor substrate; isolation trenches disposed in the substrate; digit lines each disposed within a respective one of the trenches; isolation segments disposed in the substrate between adjacent ones of the trenches; and pairs of adjacent memory cells, each pair bordered by a respective pair of isolation segments and a respective pair of isolation trenches, each pair including a shared source/drain region that is disposed in the substrate and coupled to one of the digit lines.

Claim 31

The memory array of claim 24, further comprising a dielectric material disposed in the isolation trenches and encapsulating the digit lines, the dielectric material having respective openings where the shared source/drain regions are coupled to the digit lines.

Claim 32

The memory array of claim 24 wherein: the trenches are substantially parallel to one another; and the isolation segments are substantially parallel to one another and are substantially orthogonal to the trenches.

Claim 33

The memory array of claim 24, further comprising: the memory cells each including, a gate insulator disposed on the substrate and adjacent to the shared source/drain region, and a gate disposed on the gate insulator; and word lines that are coupled to the gates of the memory cells according to a folded-digit-line layout.

Claim 34

A memory circuit, comprising: a semiconductor substrate; substantially parallel isolation trenches that are disposed in the substrate; digit lines that are respectively disposed within the trenches; trench insulators that are disposed within the trenches and on the digit lines, the trench insulators having openings that expose portions of the digit lines; substantially parallel isolation segments that are disposed in the substrate substantially orthogonally to the trenches such that first segments that are adjacent to a first side of a trench are offset approximately half way between second segments that are adjacent to a second side of the trench; active areas that are defined in the substrate and bounded by the trenches and segments; pairs of memory cells that are each disposed in a respective one of the active areas, each pair of cells including a common source/drain region that is disposed in the substrate and that is coupled to a respective exposed portion of one of the digit lines, each cell of the pair including a gate insulator that is disposed on the substrate and that is substantially contiguous with the common region, each cell of the pair including a gate disposed on the gate insulator.

Claim 35

A memory circuit, comprising: a semiconductor substrate; substantially parallel isolation trenches that are disposed in the substrate; digit lines that are respectively disposed within the trenches; trench insulators that are disposed within the trenches and on the digit lines, the trench insulators having openings that expose portions of the digit lines; substantially parallel isolation segments that are disposed in the substrate substantially orthogonally to the trenches such that first segments that are adjacent to a first side of a trench are offset approximately half way between second segments that are adjacent to a second side of the trench; active areas that are defined in the substrate and bounded by the trenches and segments; pairs of memory cells that are each disposed in a respective one of the active areas, each pair of cells including a common source/drain region that is disposed in the substrate and that is coupled to a respective exposed portion of one of the digit lines, each cell of the pair including a gate insulator that is disposed on the substrate and that is substantially contiguous with the common region, each cell of the pair including a gate disposed on the gate insulator.

Claim 36

The memory circuit of claim 28, further comprising word lines that are each respectively coupled to memory cells that are adjacent to the first side of a respective trench and to memory cells that are adjacent to the second side of the trench.

Claim 37

The memory circuit of claim 28, further comprising; first word lines that are each respectively coupled only to memory cells that are adjacent to the first side of a respective trench; and second word lines that are each respectively coupled only to memory cells that are adjacent to the second side of the trench.

Claim 38

The memory circuit of claim 28, further comprising word lines that are each coupled to a respective row of the memory cells, the word lines each having a sub-lithographic dimension.

Claim 39

A memory array, comprising: a semiconductor substrate; isolation trenches disposed in the substrate; conductors each disposed within a respective one of the trenches; isolation segments disposed in the substrate between adjacent ones of the trenches; and pairs of adjacent memory cells disposed in the substrate, each pair bordered by a respective pair of isolation segments and a respective pair of isolation trenches, the memory cells each being coupled to one of the conductors.

Claim 40

A memory array, comprising: a semiconductor substrate; isolation trenches disposed in the substrate; conductors each disposed within a respective one of the trenches; isolation segments disposed in the substrate between adjacent ones of the trenches; and pairs of adjacent memory cells disposed in the substrate, each pair bordered by a respective pair of isolation segments and a respective pair of isolation trenches, the memory cells each being coupled to one of the conductors.

Claim 41

The memory array of claim 32, further comprising a dielectric material disposed in the isolation trenches and encapsulating the conductors, the dielectric material having respective openings where the memory cells are coupled to the conductors.

Claim 42

The memory array of claim 32 wherein: the trenches are substantially parallel to one another; and the isolation segments are substantially parallel to one another and are substantially orthogonal to the trenches.

Claim 43

The memory array of claim 32, further comprising: the memory cells each including, a gate insulator disposed on the substrate, and a gate disposed on the gate insulator; and word lines that are coupled to the gates of the memory cells according to a folded-digit-line layout.

Claim 44

A memory circuit, comprising: a semiconductor substrate; substantially parallel isolation trenches that are disposed in the substrate; conductors that are respectively disposed within the trenches; trench insulators that are disposed within the trenches and on the conductors, the trench insulators having openings that expose portions of the conductors; substantially parallel isolation segments that are disposed in the substrate substantially orthogonally to the trenches such that first segments that are adjacent to a first side of a trench are offset approximately half way between second segments that are adjacent to a second side of the trench; active areas that are defined in the substrate and bounded by the trenches and segments; and pairs of memory cells that are each disposed in a respective one of the active areas, the memory cells each being coupled to one of the conductors, the memory cells each including a gate insulator that is disposed on the substrate and a gate disposed on the gate insulator.

Claim 45

A memory circuit, comprising: a semiconductor substrate; substantially parallel isolation trenches that are disposed in the substrate; conductors that are respectively disposed within the trenches; trench insulators that are disposed within the trenches and on the conductors, the trench insulators having openings that expose portions of the conductors; substantially parallel isolation segments that are disposed in the substrate substantially orthogonally to the trenches such that first segments that are adjacent to a first side of a trench are offset approximately half way between second segments that are adjacent to a second side of the trench; active areas that are defined in the substrate and bounded by the trenches and segments; and pairs of memory cells that are each disposed in a respective one of the active areas, the memory cells each being coupled to one of the conductors, the memory cells each including a gate insulator that is disposed on the substrate and a gate disposed on the gate insulator.

Claim 46

The memory circuit of claim 36, further comprising word lines that are each respectively coupled to memory cells that are adjacent to the first side of a respective trench and to memory cells that are adjacent to the second side of the trench.

Claim 47

The memory circuit of claim 36, further comprising; first word lines that are each respectively coupled only to memory cells that are adjacent to the first side of a respective trench; and second word lines that are each respectively coupled only to memory cells that are adjacent to the second side of the trench.

Claim 48

The memory circuit of claim 36, further comprising word lines that are each coupled to a respective row of the memory cells, the word lines each having a sub-lithographic dimension.