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US6281085B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing a semiconductor device

Assignee: SK Hynix Inc
•
Filing: 2000-06-28
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Granted: 2001-08-28
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Expires: 2020-06-28
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Abstract

Abstract There is disclosed a method of manufacturing a semiconductor device capable of solving the problems that a conventional method could not secure a sufficient beam current upon ion injection when forming a junction region at shallow thickness as the integration level of'devices becomes higher, and also it causes a short channel effect etc. The method includes forming a junction region, forming a selective epitaxial growth layer and then forming a LDD region, using a facet phenomenon occurring at the edge portion of the gate electrode when forming an elevated junction structure by use of a selective epitaxial growth method. Thus, it can obtain a junction region having a very shallow depth, accomplish a higher integration level of devices and prohibit a short channel effect.

Inventors

  • 👤 In Seok Yeo

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 14:43
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/01; H10D30/021; H10D30/027; H10D30/0275; H10D30/601; H10D30/603; H10D64/00; H10D64/01; H10D64/021

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 200 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a gate electrode consisted of a gate oxide film, a conductive layer and a first insulating film, thermal processing it under oxidization atmosphere, and forming a thermal oxide film on the upper portion of the gate oxide film and at the sidewalls of the conductive layer; forming a second insulating film on the entire structure and performing a blanket etching process to form a first insulating film spacer at the sidewalls of the gate electrode and forming a third insulating film on the entire structure in which the first insulating film spacer is formed and performing a blanket etching process to form a second insulating film spacer at the sidewalls of the first insulating film spacer; performing a high concentration ion injection process using the gate electrode. the first insulating film spacer and the second insulating film spacer as a mask, thus forming a junction region; performing a cleaning process to remove the second insulating film spacer; performing a selective epitaxial growth method to form a selective epitaxial growth layer on the exposed semiconductor device; and performing a low concentration ion injection process to form a LDD region.
Claim 2
Independent Claim 200 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a gate electrode consisted of a gate oxide film, a conductive layer and a first insulating film, thermal processing it under oxidization atmosphere, and forming a thermal oxide film on the upper portion of the gate oxide film and at the sidewalls of the conductive layer; forming a second insulating film on the entire structure and performing a blanket etching process to form a first insulating film spacer at the sidewalls of the gate electrode and forming a third insulating film on the entire structure in which the first insulating film spacer is formed and performing a blanket etching process to form a second insulating film spacer at the sidewalls of the first insulating film spacer; performing a high concentration ion injection process using the gate electrode. the first insulating film spacer and the second insulating film spacer as a mask, thus forming a junction region; performing a cleaning process to remove the second insulating film spacer; performing a selective epitaxial growth method to form a selective epitaxial growth layer on the exposed semiconductor device; and performing a low concentration ion injection process to form a LDD region.
Claim 3
Dependent Claim 31 words
The method of manufacturing a semiconductor device according to claim 1 , wherein said conductive layer is formed using any one of multi-structure of doped poly-silicon, amorphous silicon, metal and silicide.
Claim 4
Dependent Claim 25 words
The method of manufacturing a semiconductor device according to claim 1 , wherein said thermal oxide film is formed 30 through 100 Angstrom in thickness.
Claim 5
Dependent Claim 30 words
The method of manufacturing a semiconductor device according to claim 1 , wherein said first insulating film spacer is formed using a CVD oxide film or a CVD nitride film.
Claim 6
Dependent Claim 26 words
The method of manufacturing a semiconductor device according to claim 1 , wherein said first insulating film spacer is formed 100 through 200 Angstrom in thickness.
Claim 7
Dependent Claim 41 words
The method of manufacturing a semiconductor device according to claim 1 , wherein said second insulating film spacer is formed using materials that can remove only the second insulating film spacer without affecting the first insulating film spacer upon etching process.
Claim 8
Dependent Claim 29 words
The method of manufacturing a semiconductor device according to claim 1 , wherein said second insulating film spacer is formed using materials that can be removed by fluoric solution.
Claim 9
Dependent Claim 26 words
The method of manufacturing a semiconductor device according to claim 1 , wherein said second insulating film spacer is formed 300 through 800 Angstrom in thickness.
Claim 10
Dependent Claim 21 words
The method of manufacturing a semiconductor device according to claim 1 , wherein said cleaning process is performed using fluoric solution.
Claim 11
Dependent Claim 26 words
The method of manufacturing a semiconductor device according to claim 1 , wherein said selective epitaxial growth layer is formed 1000 through 1500 Angstrom in thickness.
Claim 12
Dependent Claim 34 words
The method of manufacturing a semiconductor device according to claim 1 , further including the step of performing a high concentration ion injection process using a low energy after formation of said LDD region.
Claim 13
Dependent Claim 28 words
The method of manufacturing a semiconductor device according to claim 11 , wherein said high concentration ion injection process is performed with ion concentration of 10 15 .

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-08-27 2005-02-26 2005-08-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-08-27 2009-02-26 2009-08-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-08-27 2013-02-26 2013-08-28 $7700.00 Window Closed / Lapsed

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