Use of nitric oxide surface anneal to provide reaction barrier for deposition of tantalum pentoxide

Abstract

Abstract The present invention provides a MOS structure and fabrication process for fabricating the substrate structure whereby a thin layer of silicon oxynitride, acting as a reaction barrier layer, and a tantalum pentoxide layer are formed in the gate region for controlling induction of electric charge in the gate region and thereby control the flow of current through the device. The high dielectric characteristic of the tantalum pentoxide facilitates blocking the flow of current in accordance with the applied voltage, and which in an off-state of the device, minimizes the gate leakage current. The silicon oxynitride barrier is formed by using a pre-deposition process of annealing the silicon substrate surface in a nitric oxide (NO) environment. The anneal may be a rapid thermal anneal (RTA) process for 10 seconds to 5 minutes at 400° C. to 1000° C. in the nitric oxide NO ambient. The annealing process produces the thin silicon oxynitride layer needed for depositing the tantalum pentoxide layer. After formation of the silicon oxynitride layer, the MOS structure undergoes a CVD deposition process for formation of a tantalum pentoxide layer on the silicon nitride surface. The silicon oxynitride layer formed using the pre-deposition anneal in nitric oxide (NO) (1) provides a hydrogen-free reaction barrier for depositing the tantalum pentoxide dielectric layer, (2) is formed at a lower temperature than a silicon nitride reaction barrier formed using ammonia, and (3) can function, when used alone, as a dielectric layer in applications that do not require the stringent off-state leakage current requirements. Other insulating material having a dielectric constant in the range of 25 to 80, such as titanium dioxide, may be formed over said silicon oxynitride layer for functioning as a reaction barrier layer.

Inventors

• 👤 Robert B. Ogle, Jr.

Bibliographic Details