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US6040230A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming a nano-rugged silicon-containing layer

Assignee: Texas Instruments Inc
•
Filing: 1998-03-13
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Granted: 2000-03-21
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Expires: 2018-03-13
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Abstract

Abstract An embodiment of the instant invention is a method of forming a nano-rugged silicon-containing layer, the method comprising the steps of: providing a first silicon-containing layer (steps 202 or 802); providing a patterning layer over the first silicon-containing layer (steps 204 or 804); the patterning layer comprised of an amorphous substance; providing a second silicon-containing layer (steps 206 or 808) over the patterning layer; and wherein the patterning layer creates a nano-rugged texture in the second silicon-containing layer. Preferably, the first and second silicon-containing layers are comprised of polycrystalline silicon. In an alternative embodiment, the patterning layer is comprised of a material which has small holes such that the step of providing the second silicon-containing layer utilizes the first silicon-containing layer as a seed layer through the small holes so as to form the second silicon-containing layer. In another alternative embodiment, the second silicon-containing layer is comprised of a plurality of islands of the silicon-containing material separated by voids in the material. Preferably, the patterning layer is comprised of SiO2.

Inventors

  • 👤 John Mark Anthony
  • 👤 Robert M. Wallace
  • 👤 Yi Wei
  • 👤 Glen Wilk

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 02:12
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/692; H10D1/711

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 60 words
A method of forming a nano-rugged silicon-containing layer, said method comprising the steps of: providing a first silicon-containing layer; providing a patterning layer over said first silicon-containing layer; said patterning layer comprised of an amorphous, conductive substance; providing a second silicon-containing layer over said patterning layer; and wherein said patterning layer creates a nano-rugged texture in said second silicon-containing layer.
Claim 2
Independent Claim 60 words
A method of forming a nano-rugged silicon-containing layer, said method comprising the steps of: providing a first silicon-containing layer; providing a patterning layer over said first silicon-containing layer; said patterning layer comprised of an amorphous, conductive substance; providing a second silicon-containing layer over said patterning layer; and wherein said patterning layer creates a nano-rugged texture in said second silicon-containing layer.
Claim 3
Dependent Claim 15 words
The method of claim 1, wherein said first silicon-containing layer is comprised of polycrystalline silicon.
Claim 4
Dependent Claim 49 words
The method of claim 1, wherein said patterning layer is comprised of a material which has small holes such that said step of providing said second silicon-containing layer utilizes said first silicon-containing layer as a seed layer through said small holes so as to form said second silicon-containing layer.
Claim 5
Dependent Claim 26 words
The method of claim 1, wherein said patterning layer is comprised of material selected iron the group consisting of: titanium nitride, iridium oxide, and ruthenium oxide.
Claim 6
Dependent Claim 27 words
The method of claim 1, wherein said second silicon-containing layer is comprised of a purality of islands of silicon-containing material separated by voids in said silicon-containing material.
Claim 7
Independent Claim 63 words
A method of fabricating an electrical device over a silicon-containing substrate, said method comprising the steps of: providing a first silicon-containing layer; providing a patterning layer over said first silicon-containing layer; said patterning layer (comprised of an amorphous, conductive substance; providing a second silicon-containing layer over said patterning layer; and wherein said patterning layer creates a nano-rugged texture in said second silicon-containing layer.
Claim 8
Independent Claim 63 words
A method of fabricating an electrical device over a silicon-containing substrate, said method comprising the steps of: providing a first silicon-containing layer; providing a patterning layer over said first silicon-containing layer; said patterning layer (comprised of an amorphous, conductive substance; providing a second silicon-containing layer over said patterning layer; and wherein said patterning layer creates a nano-rugged texture in said second silicon-containing layer.
Claim 9
Dependent Claim 13 words
The method of claim 6, wherein said electrical device is a storage capacitor.
Claim 10
Dependent Claim 15 words
The method of claim 7, wherein said storage capacitor is used in a memory device.

References Cited (Backward Citations)

US4549926A Cited
US5234857A Cited
US5612558A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-03-21 2003-09-20 2004-03-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-03-21 2007-09-20 2008-03-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-03-21 2011-09-20 2012-03-21 $7700.00 Window Closed / Lapsed

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