Method of forming bitline diffusion halo under gate conductor ledge

Claim 1

A method of fabricating a MOSFET device for a DRAM cell on a P-type semiconductor substrate including a halo implant region in said MOSFET device, comprising: providing a semiconductor substrate, a gate insulator layer over said semiconductor substrate, a conductor layer comprising polysilicon, an overlying silicide layer over said conductor layer, and an insulating cap over said silicide layer; patterning and etching said silicide layer and said insulating cap to expose a portion of the polysilicon conductor layer; providing insulating spacers comprising spacer material along sides of the patterned silicide layer and insulating cap; etching the resulting exposed portion of the polysilicon conductor layer; implanting node and bitline N-type diffusion regions to a first concentration; patterning a photoresist layer to protect the node diffusion region and expose the bitline diffusion region; etching resulting exposed spacer material from the side of said silicide layer and insulting cap; implanting a P-type impurity halo implant into the resulting exposed bitline diffusion region; and stripping the photoresist layer and providing an insulting spacer comprising spacer material along the exposed side of said silicide layer and insulting cap.

Claim 2

A method of fabricating a MOSFET device for a DRAM cell on a P-type semiconductor substrate including a halo implant region in said MOSFET device, comprising: providing a semiconductor substrate, a gate insulator layer over said semiconductor substrate, a conductor layer comprising polysilicon, an overlying silicide layer over said conductor layer, and an insulating cap over said silicide layer; patterning and etching said silicide layer and said insulating cap to expose a portion of the polysilicon conductor layer; providing insulating spacers comprising spacer material along sides of the patterned silicide layer and insulating cap; etching the resulting exposed portion of the polysilicon conductor layer; implanting node and bitline N-type diffusion regions to a first concentration; patterning a photoresist layer to protect the node diffusion region and expose the bitline diffusion region; etching resulting exposed spacer material from the side of said silicide layer and insulting cap; implanting a P-type impurity halo implant into the resulting exposed bitline diffusion region; and stripping the photoresist layer and providing an insulting spacer comprising spacer material along the exposed side of said silicide layer and insulting cap.

Claim 11

A method for fabricating a MOSFET device for a DRAM cell on a P-type semiconductor substrate including a halo implant region in said MOSFET device, comprising: providing a semiconductor substrate, a gate insulator layer over said semiconductor substrate, a conductor layer comprising polysilicon, an overlying silicide layer over said conductor layer, and an insulating cap over said silicide layer; patterning and etching said silicide layer and said insulating cap to expose a portion of the polysilicon conductor layer; providing insulating spacers comprising spacer material along sides of the patterned silicide layer and insulating cap; etching said conductor layer at areas of said conductor not covered by said spacer material; implanting node and bitline N-type diffusion region to a first concentration; patterning a photoresist layer to protect the node diffusion region and PFET source and drain regions and expose the bitline diffusion region and NFET source and drain regions; implanting the resulting exposed bitline N+ diffusion region to a heavier concentration than the first concentration; etching resulting exposed spacer material from the side of said silicide layer and insulting cap; forming an oxide layer on portions of the substrate and conductor layer exposed by said etching; implanting a P-type impurity halo implant into the resulting exposed bitline diffusion region and supporting NFET source and drain regions; and stripping the photoresist layer and providing an insulting spacer comprising spacer material along the resulting exposed side of said silicide layer and insulting cap.

Claim 12

A method for fabricating a MOSFET device for a DRAM cell on a P-type semiconductor substrate including a halo implant region in said MOSFET device, comprising: providing a semiconductor substrate, a gate insulator layer over said semiconductor substrate, a conductor layer comprising polysilicon, an overlying silicide layer over said conductor layer, and an insulating cap over said silicide layer; patterning and etching said silicide layer and said insulating cap to expose a portion of the polysilicon conductor layer; providing insulating spacers comprising spacer material along sides of the patterned silicide layer and insulating cap; etching said conductor layer at areas of said conductor not covered by said spacer material; implanting node and bitline N-type diffusion region to a first concentration; patterning a photoresist layer to protect the node diffusion region and PFET source and drain regions and expose the bitline diffusion region and NFET source and drain regions; implanting the resulting exposed bitline N+ diffusion region to a heavier concentration than the first concentration; etching resulting exposed spacer material from the side of said silicide layer and insulting cap; forming an oxide layer on portions of the substrate and conductor layer exposed by said etching; implanting a P-type impurity halo implant into the resulting exposed bitline diffusion region and supporting NFET source and drain regions; and stripping the photoresist layer and providing an insulting spacer comprising spacer material along the resulting exposed side of said silicide layer and insulting cap.