US6046472A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Graded LDD implant process for sub-half-micron MOS devices
Assignee: Micron Technology Inc
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Filing: 1997-10-14
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Granted: 2000-04-04
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Expires: 2017-10-14
Abstract
Abstract A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N- LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.
Inventors
- 👤 Aftab Ahmad
- 👤 Charles Dennison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 01:48
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01354; H10D64/021; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S257/00; Y10S257/90; Y10S257/917
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
305 words
A MOSFET comprising: a gate structure on a semiconductor substrate, said gate structure including a gate dielectric oxide layer having sides and a conductive layer having sides; a first sidewall structure and a second sidewall structure abutting opposing sides of said gate structure, said first sidewall structure and said second sidewall structure each including: layer of oxide on the sides of the gate dielectric oxide layer and the sides of the conductive layer; and an insulting nitride layer extending over the layer of oxide on the sides of the gate dielectric oxide layer and the conductive layer; a drain region comprising: a lightly doped region extending into said semiconductor substrate substantially below the layer of oxide and insulating nitride layer of said first sidewall structure; and a heavily doped region extending into said semiconductor substrate abutting said lightly doped region; a source region comprising: a lightly doped region extending into said semiconductor substrate substantially below the layer of oxide and insulating nitride layer of said second sidewall structure; and a heavily doped region extending into said semiconductor substrate abutting said lightly doped region; a channel area below said gate structure and defined between said drain region lightly doped region and said source region lightly doped region; said drain region further including a first grading of dopant concentration across a junction between said channel area and said drain region lightly doped region, and a second grading of dopant concentration across a junction between said drain region heavily doped region and said drain region lightly doped region; and said source region further including a first grading of dopant concentration across a junction between said channel area and said source region lightly doped region, and a second grading of dopant concentration across a junction between said source region heavily doped region and said source region lightly doped region.
Claim 2
Dependent Claim
305 words
A MOSFET comprising: a gate structure on a semiconductor substrate, said gate structure including a gate dielectric oxide layer having sides and a conductive layer having sides; a first sidewall structure and a second sidewall structure abutting opposing sides of said gate structure, said first sidewall structure and said second sidewall structure each including: layer of oxide on the sides of the gate dielectric oxide layer and the sides of the conductive layer; and an insulting nitride layer extending over the layer of oxide on the sides of the gate dielectric oxide layer and the conductive layer; a drain region comprising: a lightly doped region extending into said semiconductor substrate substantially below the layer of oxide and insulating nitride layer of said first sidewall structure; and a heavily doped region extending into said semiconductor substrate abutting said lightly doped region; a source region comprising: a lightly doped region extending into said semiconductor substrate substantially below the layer of oxide and insulating nitride layer of said second sidewall structure; and a heavily doped region extending into said semiconductor substrate abutting said lightly doped region; a channel area below said gate structure and defined between said drain region lightly doped region and said source region lightly doped region; said drain region further including a first grading of dopant concentration across a junction between said channel area and said drain region lightly doped region, and a second grading of dopant concentration across a junction between said drain region heavily doped region and said drain region lightly doped region; and said source region further including a first grading of dopant concentration across a junction between said channel area and said source region lightly doped region, and a second grading of dopant concentration across a junction between said source region heavily doped region and said source region lightly doped region.
Claim 3
Dependent Claim
24 words
The MOSFET of claim 1, wherein said drain region lightly doped region and said source region lightly doped region comprise low dosage arsenic implants.
Claim 4
Dependent Claim
24 words
The MOSFET of claim 1, wherein said drain region highly doped region and said source region highly doped region comprise high dosage arsenic implants.
Claim 5
Dependent Claim
22 words
The MOSFET of claim 1, wherein said drain region first grading and said drain region second grading comprise low dosage phosphorous implants.
Claim 6
Dependent Claim
22 words
The MOSFET of claim 1, wherein said source region first grading and said source region second grading comprise low dosage phosphorous implants.
Claim 7
Dependent Claim
145 words
A MOSFET on a semiconductor substrate having a source region and a drain region, wherein at least one of said source region and said drain region, comprising: a lightly doped region extending into said semiconductor substrate substantially below a sidewall structure abutting a side of a gate structure, said gate structure having a gate dielectric oxide layer and a conductive layer, said sidewall structure having a layer of oxide and an insulating layer extending over the layer of oxide; a heavily doped region extending into said semiconductor substrate abutting said lightly doped region; a channel area below said gate structure and abutting said lightly doped region; and a first grading of dopant concentration across a junction between said channel area and said lightly doped region; and a second grading of dopant concentration across a junction between said heavily doped region and said lightly doped region.
Claim 8
Dependent Claim
145 words
A MOSFET on a semiconductor substrate having a source region and a drain region, wherein at least one of said source region and said drain region, comprising: a lightly doped region extending into said semiconductor substrate substantially below a sidewall structure abutting a side of a gate structure, said gate structure having a gate dielectric oxide layer and a conductive layer, said sidewall structure having a layer of oxide and an insulating layer extending over the layer of oxide; a heavily doped region extending into said semiconductor substrate abutting said lightly doped region; a channel area below said gate structure and abutting said lightly doped region; and a first grading of dopant concentration across a junction between said channel area and said lightly doped region; and a second grading of dopant concentration across a junction between said heavily doped region and said lightly doped region.
Claim 9
Dependent Claim
16 words
The MOSFET of claim 6, wherein said lightly doped region comprises a low dosage arsenic implant.
Claim 10
Dependent Claim
16 words
The MOSFET of claim 6, wherein said highly doped region comprises a high dosage arsenic implant.
Claim 11
Dependent Claim
15 words
The MOSFET of claim 6, wherein said first grading comprises a low dosage phosphorous implant.
Claim 12
Dependent Claim
15 words
The MOSFET of claim 6, wherein said second grading comprises a low dosage phosphorous implant.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-04-04 | 2003-10-04 | 2004-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-04 | 2007-10-04 | 2008-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-04 | 2011-10-04 | 2012-04-04 | $7700.00 | Window Closed / Lapsed |